From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44767) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHfRf-0000AL-HY for qemu-devel@nongnu.org; Wed, 04 May 2011 13:01:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHfRe-0004x4-JG for qemu-devel@nongnu.org; Wed, 04 May 2011 13:01:03 -0400 Received: from mail-px0-f173.google.com ([209.85.212.173]:52850) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHfRe-0004ws-Bd for qemu-devel@nongnu.org; Wed, 04 May 2011 13:01:02 -0400 Received: by pxi16 with SMTP id 16so1066973pxi.4 for ; Wed, 04 May 2011 10:01:00 -0700 (PDT) Sender: Richard Henderson Message-ID: <4DC18641.2080904@twiddle.net> Date: Wed, 04 May 2011 10:00:49 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> <1304470768-16924-18-git-send-email-jcmvbkbc@gmail.com> <4DC17FCF.2090706@twiddle.net> In-Reply-To: <4DC17FCF.2090706@twiddle.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC 18/28] target-xtensa: implement exceptions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Max Filippov Cc: qemu-devel@nongnu.org On 05/04/2011 09:33 AM, Richard Henderson wrote: > This is a case where you almost certainly want to check this > condition inside QEMU and translate the opcode differently. > > See cpu_get_tb_cpu_state, which sets bits in *flags. These > flags can then be checked in tb->flags while translating. > At which point you'd avoid all the conditionalization on > the value in PS here in check_privilege and merely issue > the exception_cause. > > The ARM port is a good example for testing these sorts of bits. Actually, while the tb flags are useful, privileged instructions are usually checked by testing mmu_index, since we already have to generate different code for the TB based on which TLB entry we need to access. r~