From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:60519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QLZBO-00086b-Np for qemu-devel@nongnu.org; Sun, 15 May 2011 07:08:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QLZBN-0008Tp-Cg for qemu-devel@nongnu.org; Sun, 15 May 2011 07:08:22 -0400 Received: from fmmailgate02.web.de ([217.72.192.227]:33715) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QLZBM-0008TU-WA for qemu-devel@nongnu.org; Sun, 15 May 2011 07:08:21 -0400 Received: from smtp01.web.de ( [172.20.0.243]) by fmmailgate02.web.de (Postfix) with ESMTP id 690EC19F9511E for ; Sun, 15 May 2011 13:07:12 +0200 (CEST) Received: from [88.65.37.225] (helo=mchn199C.mchp.siemens.de) by smtp01.web.de with asmtp (TLSv1:AES256-SHA:256) (WEB.DE 4.110 #2) id 1QLZAG-0008S6-00 for qemu-devel@nongnu.org; Sun, 15 May 2011 13:07:12 +0200 Message-ID: <4DCFB3DF.1010904@web.de> Date: Sun, 15 May 2011 13:07:11 +0200 From: Jan Kiszka MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Sender: jan.kiszka@web.de Subject: [Qemu-devel] [PATCH 1/2] target-i386: Remove unused polarity arguments from APIC API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel From: Jan Kiszka Polarity of external interrupts needs to be handled in the IOAPIC. Passing it to the APIC is pointless. So remove all these arguments. Signed-off-by: Jan Kiszka --- hw/apic.c | 22 +++++++++------------- hw/apic.h | 6 ++---- hw/ioapic.c | 4 +--- trace-events | 2 +- 4 files changed, 13 insertions(+), 21 deletions(-) diff --git a/hw/apic.c b/hw/apic.c index 9febf40..a21a816 100644 --- a/hw/apic.c +++ b/hw/apic.c @@ -222,8 +222,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level) } static void apic_bus_deliver(const uint32_t *deliver_bitmask, - uint8_t delivery_mode, - uint8_t vector_num, uint8_t polarity, + uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) { APICState *apic_iter; @@ -280,18 +279,16 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask, apic_set_irq(apic_iter, vector_num, trigger_mode) ); } -void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, - uint8_t delivery_mode, uint8_t vector_num, - uint8_t polarity, uint8_t trigger_mode) +void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, + uint8_t vector_num, uint8_t trigger_mode) { uint32_t deliver_bitmask[MAX_APIC_WORDS]; trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, - polarity, trigger_mode); + trigger_mode); apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); - apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, - trigger_mode); + apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); } void cpu_set_apic_base(DeviceState *d, uint64_t val) @@ -548,7 +545,7 @@ void apic_sipi(DeviceState *d) static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, - uint8_t polarity, uint8_t trigger_mode) + uint8_t trigger_mode) { APICState *s = DO_UPCAST(APICState, busdev.qdev, d); uint32_t deliver_bitmask[MAX_APIC_WORDS]; @@ -591,8 +588,7 @@ static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, return; } - apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, - trigger_mode); + apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); } int apic_get_interrupt(DeviceState *d) @@ -794,7 +790,7 @@ static void apic_send_msi(target_phys_addr_t addr, uint32_t data) uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; /* XXX: Ignore redirection hint. */ - apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode); + apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) @@ -855,7 +851,7 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) s->icr[0] = val; apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), - (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); + (s->icr[0] >> 15) & 1); break; case 0x31: s->icr[1] = val; diff --git a/hw/apic.h b/hw/apic.h index 8a0c9d0..a5c910f 100644 --- a/hw/apic.h +++ b/hw/apic.h @@ -4,10 +4,8 @@ #include "qemu-common.h" /* apic.c */ -void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, - uint8_t delivery_mode, - uint8_t vector_num, uint8_t polarity, - uint8_t trigger_mode); +void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, + uint8_t vector_num, uint8_t trigger_mode); int apic_accept_pic_intr(DeviceState *s); void apic_deliver_pic_intr(DeviceState *s, int level); int apic_get_interrupt(DeviceState *s); diff --git a/hw/ioapic.c b/hw/ioapic.c index 6c26e82..5916387 100644 --- a/hw/ioapic.c +++ b/hw/ioapic.c @@ -104,7 +104,6 @@ static void ioapic_service(IOAPICState *s) uint64_t entry; uint8_t dest; uint8_t dest_mode; - uint8_t polarity; for (i = 0; i < IOAPIC_NUM_PINS; i++) { mask = 1 << i; @@ -116,7 +115,6 @@ static void ioapic_service(IOAPICState *s) dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK; - polarity = (entry >> IOAPIC_LVT_POLARITY_SHIFT) & 1; if (trig_mode == IOAPIC_TRIGGER_EDGE) { s->irr &= ~mask; } else { @@ -128,7 +126,7 @@ static void ioapic_service(IOAPICState *s) vector = entry & IOAPIC_VECTOR_MASK; } apic_deliver_irq(dest, dest_mode, delivery_mode, - vector, polarity, trig_mode); + vector, trig_mode); } } } diff --git a/trace-events b/trace-events index a00b63c..fa5b62e 100644 --- a/trace-events +++ b/trace-events @@ -76,7 +76,7 @@ disable balloon_event(void *opaque, unsigned long addr) "opaque %p addr %lu" # hw/apic.c disable apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d" -disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t polarity, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d polarity %d trigger_mode %d" +disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d" disable cpu_set_apic_base(uint64_t val) "%016"PRIx64"" disable cpu_get_apic_base(uint64_t val) "%016"PRIx64"" disable apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" -- 1.7.1