From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN3km-0006Px-GM for qemu-devel@nongnu.org; Thu, 19 May 2011 09:59:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QN3kk-0002fk-Rd for qemu-devel@nongnu.org; Thu, 19 May 2011 09:59:04 -0400 Received: from mail-yx0-f173.google.com ([209.85.213.173]:42221) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN3kk-0002fV-PF for qemu-devel@nongnu.org; Thu, 19 May 2011 09:59:02 -0400 Received: by yxk8 with SMTP id 8so1062223yxk.4 for ; Thu, 19 May 2011 06:59:02 -0700 (PDT) Message-ID: <4DD52224.1020707@codemonkey.ws> Date: Thu, 19 May 2011 08:59:00 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <4DD3C5B9.1080908@redhat.com> <4DD3D236.90708@siemens.com> <4DD3D95E.2060105@redhat.com> <4DD3E1B3.3020405@siemens.com> <4DD3E610.1080201@siemens.com> <4DD4199E.2000702@codemonkey.ws> <4DD41DBB.2020108@web.de> <20110519082644.GC28399@redhat.com> <4DD4D53F.1090108@web.de> <4DD4D88B.3070101@redhat.com> In-Reply-To: <4DD4D88B.3070101@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC] Memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Peter Maydell , Jan Kiszka , qemu-devel , Gleb Natapov On 05/19/2011 03:44 AM, Avi Kivity wrote: > On 05/19/2011 11:30 AM, Jan Kiszka wrote: >> >> >> >> That's not that simple. We need to tell apart: >> >> - if a cpu issued the request, and which one => forward to APIC >> > And cpu mode may affect where access is forwarded to. If cpu is in SMM >> > mode access to frame buffer may be forwarded to a memory (depends on >> > chipset configuration). >> >> So we have a second use case for CPU-local I/O regions? >> >> I wonder if only a single CPU can enter SMM or if all have to. Right now >> only the first CPU can switch to that mode, and that affects the >> behaviour of the chipset /wrt SMRAM mapping. Is that another hack? > > It's a hack. SMM is a per-cpu setting. Effectively it's another address > pin - it changes the meaning of (potentially) all addresses. Hrm, this may be splitting hairs, but the chipset enables SMM globally. The processor can enable it by raising a pin but there is only a single pin. It may raise/lower the pin on every load/store, but from the chipset's perspective, it's a global setting (at least in the i440fx). Regards, Anthony Liguori >