From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:38601) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN40s-0000RL-Cg for qemu-devel@nongnu.org; Thu, 19 May 2011 10:15:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QN40r-0005WP-4w for qemu-devel@nongnu.org; Thu, 19 May 2011 10:15:42 -0400 Received: from mail-yw0-f45.google.com ([209.85.213.45]:38620) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN40r-0005WL-2c for qemu-devel@nongnu.org; Thu, 19 May 2011 10:15:41 -0400 Received: by ywl41 with SMTP id 41so1070756ywl.4 for ; Thu, 19 May 2011 07:15:40 -0700 (PDT) Message-ID: <4DD5260A.1080309@codemonkey.ws> Date: Thu, 19 May 2011 09:15:38 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <4DD3D236.90708@siemens.com> <4DD3D95E.2060105@redhat.com> <4DD3E1B3.3020405@siemens.com> <4DD3E47F.9060104@redhat.com> <4DD3E782.8090208@siemens.com> <4DD3E8D6.6090807@redhat.com> <20110519090851.GD28399@redhat.com> <4DD4DE8E.8030402@redhat.com> <20110519091404.GE28399@redhat.com> <4DD5029D.6000700@redhat.com> <20110519115405.GG28399@redhat.com> <4DD505C4.6010604@redhat.com> <4DD50B17.7000205@siemens.com> <4DD511FB.3080901@redhat.com> <4DD51413.1050202@siemens.com> <4DD51468.7050509@redhat.com> <4DD51531.7000701@siemens.com> <4DD515F9.1020902@redhat.com> <4DD51A82.7060205@siemens.com> <4DD51B64.8000306@redhat.com> <4DD51FDA.3010107@codemonkey.ws> <4DD520ED.8010606@redhat.com> In-Reply-To: <4DD520ED.8010606@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC] Memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Jan Kiszka , qemu-devel , Gleb Natapov On 05/19/2011 08:53 AM, Avi Kivity wrote: > On 05/19/2011 04:49 PM, Anthony Liguori wrote: >> On 05/19/2011 08:30 AM, Avi Kivity wrote: >>> On 05/19/2011 04:26 PM, Jan Kiszka wrote: >>>> On 2011-05-19 15:07, Avi Kivity wrote: >> >>>> And when introducing hierarchical registration, we will have to go >>>> through all of this once again. Plus the API may have to be changed >>>> again if it does not fulfill all requirements of the hierarchical >>>> region >>>> management. And we have no proof that it allows an efficient core >>>> implementation. >>> >>> This API *is* hierarchical registration. v2 will (hopefully) prove that >>> it can be done efficiently. >> >> We also need hierarchical dispatch. Priorities are just a weak attempt >> to emulate hierarchical dispatch but I don't think there's an >> improvement over a single dispatch table. >> >> Hierarchical dispatch is simpler. You just need a simple list at each >> bus. >> > > The API itself says nothing about whether the hierarchy is evaluated at > run-time or registration time. Except for priorities. If you've got a hierarchy like: - CPU:0 - i440fx:1 - PIIX3:2 - ISA:3 - DeviceA - PCI:2 - DeviceB In your model, the default priorities are as shown, but nothing stops DeviceB from registering with a priority of 0 which means it can intercept accesses that would normally go to the i440fx. This is impossible in a hierarchical dispatch model. There is no setting that a PCI device can use to trap accesses that the i440fx would normally take. I don't mind if we don't have hierarchical dispatch to start with, but priorities are fundamentally broken. > We could easily have the implementation > walk the memory hierarchy to dispatch an mmio. > > However, RAM cannot be dispatched this way (we need to resolve which > ranges are RAM when the regions are registered, not accessed) so a data > structure that contains all of the information is mandatory. There is only one device that is capable of affecting the view of RAM--the i440fx PMC. The reason is simple, the i440fx is the thing that sends a request from a CPU either to a DIMM or to some device. It doesn't know which device it goes to and it doesn't care. That's where the RAM mapping lives. It doesn't matter how the PCI I/O window is split up. You don't need that information to know where RAM is. Regards, Anthony Liguori