From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34993) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN46c-0003sp-Sg for qemu-devel@nongnu.org; Thu, 19 May 2011 10:21:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QN46b-0006qW-N3 for qemu-devel@nongnu.org; Thu, 19 May 2011 10:21:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:12439) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN46b-0006qR-Ch for qemu-devel@nongnu.org; Thu, 19 May 2011 10:21:37 -0400 Message-ID: <4DD5276C.8050405@redhat.com> Date: Thu, 19 May 2011 17:21:32 +0300 From: Avi Kivity MIME-Version: 1.0 References: <4DD3D236.90708@siemens.com> <4DD3D95E.2060105@redhat.com> <4DD3E1B3.3020405@siemens.com> <4DD3E47F.9060104@redhat.com> <4DD3E782.8090208@siemens.com> <4DD3E8D6.6090807@redhat.com> <20110519090851.GD28399@redhat.com> <4DD4DE8E.8030402@redhat.com> <20110519091404.GE28399@redhat.com> <4DD5029D.6000700@redhat.com> <20110519115405.GG28399@redhat.com> <4DD505C4.6010604@redhat.com> <4DD50B17.7000205@siemens.com> <4DD511FB.3080901@redhat.com> <4DD51413.1050202@siemens.com> <4DD51468.7050509@redhat.com> <4DD51531.7000701@siemens.com> <4DD515F9.1020902@redhat.com> <4DD51A82.7060205@siemens.com> <4DD51B64.8000306@redhat.com> <4DD51FDA.3010107@codemonkey.ws> <4DD520ED.8010606@redhat.com> <4DD5260A.1080309@codemonkey.ws> In-Reply-To: <4DD5260A.1080309@codemonkey.ws> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC] Memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Jan Kiszka , qemu-devel , Gleb Natapov On 05/19/2011 05:15 PM, Anthony Liguori wrote: > > Except for priorities. > > If you've got a hierarchy like: > > - CPU:0 > - i440fx:1 > - PIIX3:2 > - ISA:3 > - DeviceA > - PCI:2 > - DeviceB > > In your model, the default priorities are as shown, but nothing stops > DeviceB from registering with a priority of 0 which means it can > intercept accesses that would normally go to the i440fx. Priorities are only within the parent region. DeviceB's priorities have no effect whatsoever since it is an only child. (and btw the intent is to have higher priorities hide lower priorities). The model is that of a nested window system with transparent windows. > > This is impossible in a hierarchical dispatch model. There is no > setting that a PCI device can use to trap accesses that the i440fx > would normally take. > > I don't mind if we don't have hierarchical dispatch to start with, but > priorities are fundamentally broken. Are not. > >> We could easily have the implementation >> walk the memory hierarchy to dispatch an mmio. >> >> However, RAM cannot be dispatched this way (we need to resolve which >> ranges are RAM when the regions are registered, not accessed) so a data >> structure that contains all of the information is mandatory. > > There is only one device that is capable of affecting the view of > RAM--the i440fx PMC. The reason is simple, the i440fx is the thing > that sends a request from a CPU either to a DIMM or to some device. > It doesn't know which device it goes to and it doesn't care. > > That's where the RAM mapping lives. It doesn't matter how the PCI I/O > window is split up. You don't need that information to know where RAM > is. There is also RAM in the framebuffer and the vga windows. It moves around. -- error compiling committee.c: too many arguments to function