From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:54801) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNBKU-0002uF-Nn for qemu-devel@nongnu.org; Thu, 19 May 2011 18:04:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QNBKT-0001VV-Ir for qemu-devel@nongnu.org; Thu, 19 May 2011 18:04:26 -0400 Received: from mail-gx0-f173.google.com ([209.85.161.173]:43065) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNBKT-0001VR-CZ for qemu-devel@nongnu.org; Thu, 19 May 2011 18:04:25 -0400 Received: by gxk26 with SMTP id 26so1279645gxk.4 for ; Thu, 19 May 2011 15:04:24 -0700 (PDT) Sender: Richard Henderson Message-ID: <4DD593E6.1060704@twiddle.net> Date: Thu, 19 May 2011 15:04:22 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> <1305671572-5899-22-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1305671572-5899-22-git-send-email-jcmvbkbc@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 21/26] target-xtensa: implement unaligned exception option List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Max Filippov Cc: qemu-devel@nongnu.org On 05/17/2011 03:32 PM, Max Filippov wrote: > See ISA, 4.4.4 for details. > > Correct (aligned as per ISA) address for unaligned access is generated > in case this option is not enabled. > > Signed-off-by: Max Filippov > --- > target-xtensa/translate.c | 33 +++++++++++++++++++++++++++++++-- > 1 files changed, 31 insertions(+), 2 deletions(-) > > diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c > index 592072a..6e66f3f 100644 > --- a/target-xtensa/translate.c > +++ b/target-xtensa/translate.c > @@ -177,6 +177,16 @@ static void gen_exception_cause(DisasContext *dc, uint32_t cause) > tcg_temp_free(_cause); > } > > +static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause, > + TCGv_i32 vaddr) > +{ > + TCGv_i32 _pc = tcg_const_i32(dc->pc); > + TCGv_i32 _cause = tcg_const_i32(cause); > + gen_helper_exception_cause_vaddr(_pc, _cause, vaddr); > + tcg_temp_free(_pc); > + tcg_temp_free(_cause); > +} > + > static void gen_check_privilege(DisasContext *dc) > { > if (dc->mem_idx) { > @@ -349,6 +359,20 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) > } > } > > +static void gen_load_store_alignment(DisasContext *dc, int shift, TCGv_i32 addr) > +{ > + TCGv_i32 tmp = tcg_temp_local_new_i32(); > + tcg_gen_mov_i32(tmp, addr); > + tcg_gen_andi_i32(addr, addr, ~0 << shift); > + if (option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { > + int label = gen_new_label(); > + tcg_gen_brcond_i32(TCG_COND_EQ, addr, tmp, label); > + gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, tmp); > + gen_set_label(label); > + } > + tcg_temp_free(tmp); > +} This is not the correct method for this. Set ALIGNED_ONLY before defining the softmmu_templates. Define do_unaligned_access to raise the exception. See e.g. target-sparc/op_helper.c. r~