From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33389) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNQjU-0005sy-Mx for qemu-devel@nongnu.org; Fri, 20 May 2011 10:31:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QNQjT-0006GG-LQ for qemu-devel@nongnu.org; Fri, 20 May 2011 10:31:16 -0400 Received: from mail-yw0-f45.google.com ([209.85.213.45]:59362) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNQjT-0006Fz-8a for qemu-devel@nongnu.org; Fri, 20 May 2011 10:31:15 -0400 Received: by ywl41 with SMTP id 41so1529574ywl.4 for ; Fri, 20 May 2011 07:31:14 -0700 (PDT) Message-ID: <4DD67B2F.5080907@codemonkey.ws> Date: Fri, 20 May 2011 09:31:11 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <1305814352-15044-1-git-send-email-avi@redhat.com> <1305814352-15044-2-git-send-email-avi@redhat.com> <4DD580FD.2030409@codemonkey.ws> <4DD6331E.8000105@redhat.com> <4DD67563.9080803@twiddle.net> In-Reply-To: <4DD67563.9080803@twiddle.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC v1] Add declarations for hierarchical memory region API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Avi Kivity , kvm@vger.kernel.org, qemu-devel@nongnu.org On 05/20/2011 09:06 AM, Richard Henderson wrote: > On 05/20/2011 02:23 AM, Avi Kivity wrote: >> On 05/19/2011 11:43 PM, Anthony Liguori wrote: >>> On 05/19/2011 09:12 AM, Avi Kivity wrote: >>>> The memory API separates the attributes of a memory region (its size, how >>>> reads or writes are handled, dirty logging, and coalescing) from where it >>>> is mapped and whether it is enabled. This allows a device to configure >>>> a memory region once, then hand it off to its parent bus to map it according >>>> to the bus configuration. >>>> >>>> Hierarchical registration also allows a device to compose a region out of >>>> a number of sub-regions with different properties; for example some may be >>>> RAM while others may be MMIO. >>>> >>>> + struct { >>>> + /* If nonzero, specify bounds on access sizes beyond which a machine >>>> + * check is thrown. >>>> + */ >>>> + unsigned min_access_size; >>>> + unsigned max_access_size; >>>> + /* If true, unaligned accesses are supported. Otherwise unaligned >>>> + * accesses throw machine checks. >>>> + */ >>>> + bool unaligned; >>>> + } valid; >>> >>> Under what circumstances would this be used? >>> >>> The behavior of devices that receive non-natural accesses varies wildly. >>> >>> For PCI devices, invalid accesses almost always return ~0. I can't think of a device where an MCE would occur. >> >> This was requested by Richard, so I'll let him comment. >> > > Several alpha system chips MCE when accessed with incorrect sizes. > E.g. only 64-bit accesses are allowed. But is this a characteristic of devices or is this a characteristic of the chipset/CPU? At any rate, I'm fairly sure it doesn't belong in the MemoryRegion structure. Regards, Anthony Liguori