From: john cooper <john.cooper@redhat.com>
To: qemu-devel@nongnu.org
Cc: john cooper <john.cooper@redhat.com>,
Anthony Liguori <aliguori@us.ibm.com>
Subject: [Qemu-devel] [PATCH 1/7] cpu model bug fixes and definition corrections: Correct archaic CPU model "model" field for Intel CPUs.
Date: Mon, 23 May 2011 17:46:25 -0400 [thread overview]
Message-ID: <4DDAD5B1.7010800@redhat.com> (raw)
Correct archaic CPU model "model" field for Intel CPUs.
The old "model" values caused two known problems:
- Skype crashes on a winxp guest if model < 6, due to syscall vs.
sysenter confusion.
- 32 bit windows doesn't enable MSI support if model < 13.
After consulting with Intel the following recommendations were
received which more accurately represent shipped silicon.
Signed-off-by: john cooper <john.cooper@redhat.com>
---
diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index 43ad282..0613870 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -5,7 +5,7 @@
level = "2"
vendor = "GenuineIntel"
family = "6"
- model = "2"
+ model = "15"
stepping = "3"
feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36"
feature_ecx = "sse3 ssse3"
@@ -19,7 +19,7 @@
level = "2"
vendor = "GenuineIntel"
family = "6"
- model = "2"
+ model = "23"
stepping = "3"
feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36"
feature_ecx = "sse3 cx16 ssse3 sse4.1"
@@ -33,7 +33,7 @@
level = "2"
vendor = "GenuineIntel"
family = "6"
- model = "2"
+ model = "26"
stepping = "3"
feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu mtrr clflush mca pse36"
feature_ecx = "sse3 cx16 ssse3 sse4.1 sse4.2 popcnt"
--
john.cooper@redhat.com
reply other threads:[~2011-05-23 22:09 UTC|newest]
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