From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([140.186.70.92]:57278)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1QOt4w-0003jP-23
	for qemu-devel@nongnu.org; Tue, 24 May 2011 10:59:27 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1QOt4v-0001Gf-96
	for qemu-devel@nongnu.org; Tue, 24 May 2011 10:59:26 -0400
Received: from mail-px0-f173.google.com ([209.85.212.173]:53998)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1QOt4v-0001GX-4X
	for qemu-devel@nongnu.org; Tue, 24 May 2011 10:59:25 -0400
Received: by pxi16 with SMTP id 16so4446565pxi.4
	for <qemu-devel@nongnu.org>; Tue, 24 May 2011 07:59:23 -0700 (PDT)
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <4DDBC7C9.4060808@twiddle.net>
Date: Tue, 24 May 2011 07:59:21 -0700
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com>	<201105210005.00438.jcmvbkbc@gmail.com>	<4DD6D3CE.1070701@twiddle.net>	<201105210130.11067.jcmvbkbc@gmail.com>	<4DD6E8DD.4020309@twiddle.net>
	<BANLkTin3hbbvZ5CjC_b2QVtoN+veOp00yw@mail.gmail.com>
In-Reply-To: <BANLkTin3hbbvZ5CjC_b2QVtoN+veOp00yw@mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH 23/26] target-xtensa: implement interrupt
 option
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Max Filippov <jcmvbkbc@gmail.com>
Cc: qemu-devel@nongnu.org

On 05/24/2011 03:28 AM, Max Filippov wrote:
>>> - cycles fed into advance_ccount may (and on real hardware actually
>>> do) depend on executed commands/pipeline/cache hits. Most of this
>>> stuff may be counted at the translation time;
>>
>> Since CCOUNT, as seen by any one thread of execution, on real hw depends
>> on cache hits, interrupts, and other asynchronous stuff, then don't bother
>> trying to account for it on a per-instruction basis.  Just define a clock
>> that runs at a given rate and be done.  No need to advance it manually.
> 
> It means no cycle-accurate emulation. This was one of my goals, maybe
> not closest one. Is it acceptable to have two simulation modes -- fast
> functional and slower cycle-accurate?

Huh.  Given that you're not modeling the caches, I don't see how you could
hope for true cycle accuracy.  As for whether a mostly-cycle-accurate mode
should be a goal...  I'll have to defer to other QEMU maintainers.


r~