From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:54672) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRRIb-0001xY-MX for qemu-devel@nongnu.org; Tue, 31 May 2011 11:56:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QRRIZ-0005CQ-Pi for qemu-devel@nongnu.org; Tue, 31 May 2011 11:56:05 -0400 Received: from agogare.doit.wisc.edu ([144.92.197.211]:48868) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRRIZ-0005CI-MW for qemu-devel@nongnu.org; Tue, 31 May 2011 11:56:03 -0400 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; CHARSET=US-ASCII; format=flowed Received: from avs-daemon.smtpauth2.wiscmail.wisc.edu by smtpauth2.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 7u2-7.05 32bit (built Jul 30 2009)) id <0LM200M00ETE2700@smtpauth2.wiscmail.wisc.edu> for qemu-devel@nongnu.org; Tue, 31 May 2011 09:56:02 -0500 (CDT) Received: from comporellon.tachypleus.net (adsl-71-150-248-94.dsl.mdsnwi.sbcglobal.net [71.150.248.94]) by smtpauth2.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 7u2-7.05 32bit (built Jul 30 2009)) with ESMTPSA id <0LM200FUXETDMM10@smtpauth2.wiscmail.wisc.edu> for qemu-devel@nongnu.org; Tue, 31 May 2011 09:56:01 -0500 (CDT) Date: Tue, 31 May 2011 09:56:01 -0500 From: Nathan Whitehorn Message-id: <4DE50181.6070902@freebsd.org> Subject: [Qemu-devel] [PATCH] ppc64: fix mtmsr behavior on 64-bit targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The mtmsr instruction is required not to modify the upper 32-bits of the machine state register, but checks the current value of MSR[SF] to decide whether to do this. This has the effect of zeroing the upper 32 bits of the MSR whenever mtmsr is executed in 64-bit mode. Unconditionally preserve the upper 32-bits in mtmsr for TARGET_PPC64. --- target-ppc/translate.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9b3f90c..a60dbe9 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3886,7 +3886,6 @@ static void gen_mtmsr(DisasContext *ctx) */ gen_update_nip(ctx, ctx->nip); #if defined(TARGET_PPC64) - if (!ctx->sf_mode) { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL); @@ -3895,9 +3894,9 @@ static void gen_mtmsr(DisasContext *ctx) tcg_temp_free(t1); gen_helper_store_msr(t0); tcg_temp_free(t0); - } else -#endif +#else gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); +#endif /* Must stop the translation as machine state (may have) changed */ /* Note that mtmsr is not always defined as context-synchronizing */ gen_stop_exception(ctx);