From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:58514) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRn3I-0006rr-GI for qemu-devel@nongnu.org; Wed, 01 Jun 2011 11:09:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QRn39-0007p9-UO for qemu-devel@nongnu.org; Wed, 01 Jun 2011 11:09:43 -0400 Received: from mail-gy0-f173.google.com ([209.85.160.173]:43690) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRn39-0007og-AK for qemu-devel@nongnu.org; Wed, 01 Jun 2011 11:09:35 -0400 Received: by gyg4 with SMTP id 4so2677139gyg.4 for ; Wed, 01 Jun 2011 08:09:34 -0700 (PDT) Sender: Richard Henderson Message-ID: <4DE65629.1010300@twiddle.net> Date: Wed, 01 Jun 2011 08:09:29 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1306892315-7306-1-git-send-email-eduard.munteanu@linux360.ro> <1306892315-7306-2-git-send-email-eduard.munteanu@linux360.ro> <4DE64646.3010505@twiddle.net> <20110601145227.GA2936@localhost> In-Reply-To: <20110601145227.GA2936@localhost> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH 01/13] Generic DMA memory access interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduard - Gabriel Munteanu Cc: aliguori@us.ibm.com, kvm@vger.kernel.org, mst@redhat.com, aik@ozlabs.ru, joro@8bytes.org, seabios@seabios.org, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, yamahata@valinux.co.jp, paul@codesourcery.com, kevin@koconnor.net, avi@redhat.com, dwg@au1.ibm.com, david@gibson.dropbear.id.au On 06/01/2011 07:52 AM, Eduard - Gabriel Munteanu wrote: > The main selling point is there are more chances to screw up if every > bus layer implements these manually. And it's really convenient, > especially if we get to add another ld/st. If we drop the ld/st, we're talking about 5 lines for every bus layer. If I recall, there was just the one driver that actually uses the ld/st interface; most used the read/write interface. > If I understand correctly you need some sort of shared state between > IOMMUs or units residing on different buses. Then you should be able to > get to it even with this API, just like I do with my AMD IOMMU state by > upcasting. It doesn't seem to matter whether you've got an opaque, that > opaque could very well be reachable by upcasting. > > Did I get this wrong? Can you honestly tell me that > +static int amd_iommu_translate(DMADevice *dev, > + dma_addr_t addr, > + dma_addr_t *paddr, > + dma_addr_t *len, > + int is_write) > +{ > + PCIDevice *pci_dev = container_of(dev, PCIDevice, dma); > + PCIDevice *iommu_dev = DO_UPCAST(PCIDevice, qdev, dev->mmu->iommu); > + AMDIOMMUState *s = DO_UPCAST(AMDIOMMUState, dev, iommu_dev); THREE (3) upcasts is a sane to write maintainable software? The margin for error here is absolutely enormous. If you had just passed in that AMDIOMMUState* as the opaque value, it would be trivial to look at the initialization statement and the callback function to verify that the right value is being passed. r~