From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRqUY-0007pM-76 for qemu-devel@nongnu.org; Wed, 01 Jun 2011 14:50:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QRqUU-0000TF-Rp for qemu-devel@nongnu.org; Wed, 01 Jun 2011 14:50:05 -0400 Received: from mail-yw0-f45.google.com ([209.85.213.45]:53183) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRqUU-0000T6-Cd for qemu-devel@nongnu.org; Wed, 01 Jun 2011 14:50:02 -0400 Received: by ywl41 with SMTP id 41so53657ywl.4 for ; Wed, 01 Jun 2011 11:50:01 -0700 (PDT) Sender: Richard Henderson Message-ID: <4DE689D5.3090007@twiddle.net> Date: Wed, 01 Jun 2011 11:49:57 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1306892315-7306-1-git-send-email-eduard.munteanu@linux360.ro> In-Reply-To: <1306892315-7306-1-git-send-email-eduard.munteanu@linux360.ro> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH 00/13] AMD IOMMU emulation patches, another try List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduard - Gabriel Munteanu Cc: aliguori@us.ibm.com, kvm@vger.kernel.org, mst@redhat.com, aik@ozlabs.ru, joro@8bytes.org, seabios@seabios.org, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, yamahata@valinux.co.jp, paul@codesourcery.com, kevin@koconnor.net, avi@redhat.com, dwg@au1.ibm.com, david@gibson.dropbear.id.au On 05/31/2011 06:38 PM, Eduard - Gabriel Munteanu wrote: > Hi, > > Again, sorry for taking so long, but I just don't send stuff without looking > through it. This is meant to go into Michael's PCI branch, if it does. > > Some of the changes include: > - some fixes (one thanks to David Gibson) and cleanups > - macro magic for exporting clones of the DMA interface (e.g. > pci_memory_read()); I hope it isn't too much a stretch > - we use pci_memory_*() in most places where PCI devices are involved now > - luckily we don't need unaligned accesses anymore > - some attempt at signaling target aborts, but it doesn't seem like that > stuff is completely implemented in the PCI layer / devices > - PCI ids are defined in hw/amd_iommu.c until they get merged into Linux > > Also, I can't answer every request that the API is extended for doing this and > that more comfortably. I understand there may be corner cases, but may I > suggest merging it (maybe into a separate branch related to mst's pci) so that > everybody can deal with it? This is still labeled RFC, but if you think it's > ready it can be merged. > > I hope most of the important issues have been dealt with. I'll post the SeaBIOS > patches soon (though I think you can give it a spin with the old ones, if you > need). I'll also take care of submitting PCI ids to be merged into Linux. > > In any case, let me know what you think. I hope I didn't forget to Cc someone. In order to move the discussion along productively, please have a look at git://repo.or.cz/qemu/rth.git axp-iommu-1 which is based on your previous patch set. There's stuff in there that's not 100% relevant to the discussion, but these two commits: 0652a74 target-alpha: Implement iommu translation for Typhoon. db50b11 DMA: Use an void* opaque value, rather than upcasting from qdev. are exactly what I'm interested in discussing. r~