From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:54945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QSwW6-0004pj-No for qemu-devel@nongnu.org; Sat, 04 Jun 2011 15:28:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QSwW5-0000f2-QQ for qemu-devel@nongnu.org; Sat, 04 Jun 2011 15:28:14 -0400 Received: from argol.doit.wisc.edu ([144.92.197.212]:63204) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QSwW5-0000eu-NN for qemu-devel@nongnu.org; Sat, 04 Jun 2011 15:28:13 -0400 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; CHARSET=US-ASCII; format=flowed Received: from avs-daemon.smtpauth3.wiscmail.wisc.edu by smtpauth3.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 7u2-7.05 32bit (built Jul 30 2009)) id <0LMA00D0062ZQA00@smtpauth3.wiscmail.wisc.edu> for qemu-devel@nongnu.org; Sat, 04 Jun 2011 14:28:11 -0500 (CDT) Date: Sat, 04 Jun 2011 14:28:09 -0500 From: Nathan Whitehorn In-reply-to: <4DE52823.4000805@twiddle.net> Message-id: <4DEA8749.6090902@freebsd.org> References: <4DE50181.6070902@freebsd.org> <4DE52823.4000805@twiddle.net> Subject: Re: [Qemu-devel] [PATCH] ppc64: fix mtmsr behavior on 64-bit targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On 05/31/11 12:40, Richard Henderson wrote: > On 05/31/2011 07:56 AM, Nathan Whitehorn wrote: >> #if defined(TARGET_PPC64) >> - if (!ctx->sf_mode) { >> TCGv t0 = tcg_temp_new(); >> TCGv t1 = tcg_temp_new(); > You're removing a scope in which these variables were defined. > That seems wrong, at minimum. > I'll fix that (and resend the patch), thanks. A note on this: it looks like a lot of code here incorrectly changes behavior depending on the setting of MSR[SF]. While most of them aren't checking the condition the wrong way, like here, MSR[SF] actually changes very few aspects of the processor's operation. Turning MSR[SF] on or off on a 64-bit CPU basically only affects whether it pays attention to the high 32-bits of addresses when doing loads, stores, and branches -- 64-bit arithmetic, comparisons, registers, etc. are all available whatever the setting of MSR[SF]. -Nathan