From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52174) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QTCxG-0004of-JZ for qemu-devel@nongnu.org; Sun, 05 Jun 2011 09:01:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QTCxF-0000Q5-JG for qemu-devel@nongnu.org; Sun, 05 Jun 2011 09:01:22 -0400 Received: from host-82-135-62-35.customer.m-online.net ([82.135.62.35]:46927 helo=mail.embedded-brains.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QTCxF-0000NY-Cu for qemu-devel@nongnu.org; Sun, 05 Jun 2011 09:01:21 -0400 Message-ID: <4DEB7F55.9030700@embedded-brains.de> Date: Sun, 05 Jun 2011 15:06:29 +0200 From: Sebastian Huber MIME-Version: 1.0 References: <4DEB5AFF.3010604@embedded-brains.de> In-Reply-To: <4DEB5AFF.3010604@embedded-brains.de> Content-Type: multipart/mixed; boundary="------------010904020808050905050308" Subject: Re: [Qemu-devel] Disable interrupts on Cortex M3 (lm3s6965evb) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paul Brook This is a multi-part message in MIME format. --------------010904020808050905050308 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit On 05/06/11 12:31, Sebastian Huber wrote: > Hello, > > how can I disable interrupts on the Cortex M3 based board LM3S6965EVB? > Even if I set PRIMASK, FAULTMASK and BASEPRI to 1 the SYSTICK interrupt > handler gets called. > > Have a nice day! > I think the interrupt handling logic for ARMv7M is wrong in cpu-exec.c line 470. Please have a look at the attached patch. --------------010904020808050905050308 Content-Type: text/x-patch; name="0001-Fixed-interrupt-handling-for-ARMv7M.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0001-Fixed-interrupt-handling-for-ARMv7M.patch" >>From b424c34d0202950307b3a12778a06834917b2947 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Sun, 5 Jun 2011 14:57:17 +0200 Subject: [PATCH] Fixed interrupt handling for ARMv7M. --- cpu-exec.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 6ddd8dd..2782076 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -470,8 +470,8 @@ int cpu_exec(CPUState *env1) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->uncached_cpsr & CPSR_I))) { + && !(env->uncached_cpsr & CPSR_I) + && (IS_M(env) && env->regs[15] < 0xfffffff0)) { env->exception_index = EXCP_IRQ; do_interrupt(env); next_tb = 0; -- 1.7.1 --------------010904020808050905050308--