From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:35039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QVmux-00007d-RC for qemu-devel@nongnu.org; Sun, 12 Jun 2011 11:49:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QVmuw-0000hV-8P for qemu-devel@nongnu.org; Sun, 12 Jun 2011 11:49:39 -0400 Received: from adsum.doit.wisc.edu ([144.92.197.210]:49429) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QVmuv-0000hO-SG for qemu-devel@nongnu.org; Sun, 12 Jun 2011 11:49:37 -0400 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; CHARSET=US-ASCII; format=flowed Received: from avs-daemon.smtpauth1.wiscmail.wisc.edu by smtpauth1.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 7u2-7.05 32bit (built Jul 30 2009)) id <0LMO00J00PANPE00@smtpauth1.wiscmail.wisc.edu> for qemu-devel@nongnu.org; Sun, 12 Jun 2011 10:49:35 -0500 (CDT) Date: Sun, 12 Jun 2011 10:49:33 -0500 From: Nathan Whitehorn In-reply-to: Message-id: <4DF4E00D.4030101@freebsd.org> References: <4DE50181.6070902@freebsd.org> <4DE52823.4000805@twiddle.net> <4DEA8749.6090902@freebsd.org> <1EA846CC-A2F8-4677-9012-ACEEC78F3B12@suse.de> <4DEB8597.8050906@freebsd.org> Subject: [Qemu-devel] [PATCH2] ppc64: fix mtmsr behavior on 64-bit targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexander Graf The mtmsr instruction is required not to modify the upper 32-bits of the machine state register, but checks the current value of MSR[SF] to decide whether to do this. This has the effect of zeroing the upper 32 bits of the MSR whenever mtmsr is executed in 64-bit mode. Unconditionally preserve the upper 32-bits in mtmsr for TARGET_PPC64. Signed-off-by: Nathan Whitehorn --- target-ppc/translate.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 59aef85..38d2e2e 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3884,18 +3884,17 @@ static void gen_mtmsr(DisasContext *ctx) */ gen_update_nip(ctx, ctx->nip); #if defined(TARGET_PPC64) - if (!ctx->sf_mode) { - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL); - tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); - gen_helper_store_msr(t0); - tcg_temp_free(t0); - } else + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL); + tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); + gen_helper_store_msr(t0); + tcg_temp_free(t0); +#else + gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); #endif - gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); /* Must stop the translation as machine state (may have) changed */ /* Note that mtmsr is not always defined as context-synchronizing */ gen_stop_exception(ctx);