From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:35442) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QVmw3-0000Qv-Oc for qemu-devel@nongnu.org; Sun, 12 Jun 2011 11:50:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QVmw2-0000vU-6q for qemu-devel@nongnu.org; Sun, 12 Jun 2011 11:50:47 -0400 Received: from adsum.doit.wisc.edu ([144.92.197.210]:49530) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QVmw1-0000vJ-Rw for qemu-devel@nongnu.org; Sun, 12 Jun 2011 11:50:46 -0400 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; CHARSET=US-ASCII; format=flowed Received: from avs-daemon.smtpauth1.wiscmail.wisc.edu by smtpauth1.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 7u2-7.05 32bit (built Jul 30 2009)) id <0LMO00J00PCLUJ00@smtpauth1.wiscmail.wisc.edu> for qemu-devel@nongnu.org; Sun, 12 Jun 2011 10:50:45 -0500 (CDT) Received: from comporellon.tachypleus.net (adsl-76-208-69-18.dsl.mdsnwi.sbcglobal.net [76.208.69.18]) by smtpauth1.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 7u2-7.05 32bit (built Jul 30 2009)) with ESMTPSA id <0LMO00CTQPCKMY00@smtpauth1.wiscmail.wisc.edu> for qemu-devel@nongnu.org; Sun, 12 Jun 2011 10:50:44 -0500 (CDT) Date: Sun, 12 Jun 2011 10:50:43 -0500 From: Nathan Whitehorn In-reply-to: <4DE500C3.80408@freebsd.org> Message-id: <4DF4E053.7050205@freebsd.org> References: <4DE500C3.80408@freebsd.org> Subject: [Qemu-devel] [PATCH2] ppc: provide PIR register on all book-S CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The PIR register is architecturally specified on all PowerPC non-embedded CPUs, but currently is only available on the 604, 620, and G4. Add it to all 601-derived CPUs. Signed-off-by: Nathan Whitehorn --- target-ppc/translate_init.c | 20 +++++--------------- 1 files changed, 5 insertions(+), 15 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index b511afa..1286ddf 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -670,6 +670,11 @@ static void gen_spr_ne_601 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_sdr1, 0x00000000); + /* Processor identification */ + spr_register(env, SPR_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + env->cpu_index); } /* BATs 0-3 */ @@ -1019,11 +1024,6 @@ static void gen_spr_thrm (CPUPPCState *env) /* SPR specific to PowerPC 604 implementation */ static void gen_spr_604 (CPUPPCState *env) { - /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); /* Breakpoints */ /* XXX : not implemented */ spr_register(env, SPR_IABR, "IABR", @@ -1259,11 +1259,6 @@ static void gen_spr_601 (CPUPPCState *env) static void gen_spr_74xx (CPUPPCState *env) { - /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_MMCR2, "MMCR2", SPR_NOACCESS, SPR_NOACCESS, @@ -2118,11 +2113,6 @@ static void gen_spr_compress (CPUPPCState *env) /* SPR specific to PowerPC 620 */ static void gen_spr_620 (CPUPPCState *env) { - /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); spr_register(env, SPR_ASR, "ASR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_asr, &spr_write_asr,