From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:35501) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QW6ct-0007IL-Eq for qemu-devel@nongnu.org; Mon, 13 Jun 2011 08:52:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QW6cs-0007Jl-FL for qemu-devel@nongnu.org; Mon, 13 Jun 2011 08:52:19 -0400 Received: from argol.doit.wisc.edu ([144.92.197.212]:34227) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QW6cs-0007JZ-B1 for qemu-devel@nongnu.org; Mon, 13 Jun 2011 08:52:18 -0400 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; CHARSET=US-ASCII; format=flowed Received: from avs-daemon.smtpauth3.wiscmail.wisc.edu by smtpauth3.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 7u2-7.05 32bit (built Jul 30 2009)) id <0LMQ00700BR5NK00@smtpauth3.wiscmail.wisc.edu> for qemu-devel@nongnu.org; Mon, 13 Jun 2011 07:52:17 -0500 (CDT) Date: Mon, 13 Jun 2011 07:52:15 -0500 From: Nathan Whitehorn In-reply-to: <39A65BD8-AC5F-4CEB-A529-6E9F9E6406DC@suse.de> Message-id: <4DF607FF.2030802@freebsd.org> References: <4DE50181.6070902@freebsd.org> <4DE52823.4000805@twiddle.net> <4DEA8749.6090902@freebsd.org> <1EA846CC-A2F8-4677-9012-ACEEC78F3B12@suse.de> <4DEB8597.8050906@freebsd.org> <4DF4E00D.4030101@freebsd.org> <39A65BD8-AC5F-4CEB-A529-6E9F9E6406DC@suse.de> Subject: Re: [Qemu-devel] [PATCH2] ppc64: fix mtmsr behavior on 64-bit targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: "qemu-devel@nongnu.org" On 06/13/11 05:20, Alexander Graf wrote: > > > > Am 12.06.2011 um 17:49 schrieb Nathan Whitehorn: > >> The mtmsr instruction is required not to modify the upper 32-bits of the machine state register, but checks the current value of MSR[SF] to decide whether to do this. This has the effect of zeroing the upper 32 bits of the MSR whenever mtmsr is executed in 64-bit mode. Unconditionally preserve the upper 32-bits in mtmsr for TARGET_PPC64. >> >> Signed-off-by: Nathan Whitehorn >> --- >> target-ppc/translate.c | 5 ++--- >> 1 files changed, 2 insertions(+), 3 deletions(-) >> >> diff --git a/target-ppc/translate.c b/target-ppc/translate.c >> index 59aef85..38d2e2e 100644 >> --- a/target-ppc/translate.c >> +++ b/target-ppc/translate.c >> @@ -3884,18 +3884,17 @@ static void gen_mtmsr(DisasContext *ctx) >> */ >> gen_update_nip(ctx, ctx->nip); >> #if defined(TARGET_PPC64) >> - if (!ctx->sf_mode) { >> - TCGv t0 = tcg_temp_new(); >> - TCGv t1 = tcg_temp_new(); >> - tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL); >> - tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); >> - tcg_gen_or_tl(t0, t0, t1); >> - tcg_temp_free(t1); >> - gen_helper_store_msr(t0); >> - tcg_temp_free(t0); >> - } else >> + TCGv t0 = tcg_temp_new(); >> + TCGv t1 = tcg_temp_new(); > You're declaring variables in mid-scope. Please open a new scope :). Does the gen_update_nip(ctx, ctx->nip); need to be first here? If not, we can just move it to the end and avoid the scoping issue. >> + tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL); >> + tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); >> + tcg_gen_or_tl(t0, t0, t1); > While at it, this is a perfect scenario for the deposit tcg op! :) > > If you feel like this is too cumbersome work for such a small patch, please let me know and I'll do the changes for you :) I have no idea what that is, so I'd prefer you do it :) -Nathan