From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:54642) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QXZY2-0006uI-3m for qemu-devel@nongnu.org; Fri, 17 Jun 2011 09:57:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QXZXv-0006s6-QR for qemu-devel@nongnu.org; Fri, 17 Jun 2011 09:57:21 -0400 Received: from am1ehsobe004.messaging.microsoft.com ([213.199.154.207]:16175 helo=AM1EHSOBE004.bigfish.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QXZXu-0006r0-WA for qemu-devel@nongnu.org; Fri, 17 Jun 2011 09:57:15 -0400 Received: from mail58-am1 (localhost.localdomain [127.0.0.1]) by mail58-am1-R.bigfish.com (Postfix) with ESMTP id 860771C200ED for ; Fri, 17 Jun 2011 09:39:01 +0000 (UTC) Received: from AM1EHSMHS011.bigfish.com (unknown [10.3.201.244]) by mail58-am1.bigfish.com (Postfix) with ESMTP id 4CAE91C4004B for ; Fri, 17 Jun 2011 09:39:01 +0000 (UTC) Received: from sausexedgep01.amd.com (sausexedgep01-ext.amd.com [163.181.249.72]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ausb3twp01.amd.com (Axway MailGate 3.8.1) with ESMTP id 2E01810282B2 for ; Fri, 17 Jun 2011 04:38:58 -0500 (CDT) Message-ID: <4DFB20B1.8070409@amd.com> Date: Fri, 17 Jun 2011 11:38:57 +0200 From: Christoph Egger MIME-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-15"; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH] target-i386: fix cmpxchg List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-devel@nongnu.org" Correct emulation of i386 cmpxchg instruction in the case where the comparison outcome is unequal and the memory write causes a page fault. From: Andreas Gustafsson Signed-off-by: Christoph Egger diff --git a/target-i386/translate.c b/target-i386/translate.c index 10bd72a..69a878f 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4857,20 +4857,23 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0); gen_extu(ot, t2); tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); + label2 = gen_new_label(); if (mod == 3) { - label2 = gen_new_label(); gen_op_mov_reg_v(ot, R_EAX, t0); tcg_gen_br(label2); gen_set_label(label1); gen_op_mov_reg_v(ot, rm, t1); - gen_set_label(label2); } else { - tcg_gen_mov_tl(t1, t0); + /* perform no-op store cycle like physical cpu; must be + * before changing accumulator to ensure idempotency if + * the store faults and the instruction is restarted */ + gen_op_st_v(ot + s->mem_index, t0, a0); gen_op_mov_reg_v(ot, R_EAX, t0); + tcg_gen_br(label2); gen_set_label(label1); - /* always store */ gen_op_st_v(ot + s->mem_index, t1, a0); } + gen_set_label(label2); tcg_gen_mov_tl(cpu_cc_src, t0); tcg_gen_mov_tl(cpu_cc_dst, t2); s->cc_op = CC_OP_SUBB + ot; -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85689 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632