From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:49927) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QY4CP-0004ff-8V for qemu-devel@nongnu.org; Sat, 18 Jun 2011 18:41:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QY4CO-0005Sr-8p for qemu-devel@nongnu.org; Sat, 18 Jun 2011 18:41:05 -0400 Received: from elasmtp-galgo.atl.sa.earthlink.net ([209.86.89.61]:51688) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QY4CN-0005Sb-RC for qemu-devel@nongnu.org; Sat, 18 Jun 2011 18:41:03 -0400 Message-ID: <4DFD297D.3010607@earthlink.net> Date: Sat, 18 Jun 2011 18:41:01 -0400 From: Robert Reif MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] Sparc32: dummy implementation of MXCC MMU breakpoint registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Bob Breuer , qemu-devel Blue Swirl wrote: > Add dummy registers for SuperSPARC MXCC MMU counter breakpoints. > > Signed-off-by: Blue Swirl > --- > target-sparc/cpu.h | 1 + > target-sparc/op_helper.c | 26 ++++++++++++++++++++++++-- > 2 files changed, 25 insertions(+), 2 deletions(-) > > diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h > index 320530e..b5d5291 100644 > --- a/target-sparc/cpu.h > +++ b/target-sparc/cpu.h > @@ -403,6 +403,7 @@ typedef struct CPUSPARCState { > uint32_t mmuregs[32]; > uint64_t mxccdata[4]; > uint64_t mxccregs[8]; > + uint32_t mmubpctrv, mmubpctrc, mmubpctrs, mmubpaction; > uint64_t mmubpregs[4]; > uint64_t prom_addr; > #endif > diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c > index b38691e..e9cc1f5 100644 > --- a/target-sparc/op_helper.c > +++ b/target-sparc/op_helper.c > @@ -1940,7 +1940,6 @@ uint64_t helper_ld_asi(target_ulong addr, int > asi, int size, int sign) > case 0x31: // Turbosparc RAM snoop > case 0x32: // Turbosparc page table descriptor diagnostic > case 0x39: /* data cache diagnostic register */ > - case 0x4c: /* SuperSPARC MMU Breakpoint Action register */ > ret = 0; > break; > case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ > @@ -1966,6 +1965,18 @@ uint64_t helper_ld_asi(target_ulong addr, int > asi, int size, int sign) > ret); > } > break; > + case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ > + ret = env->mmubpctrv; > + break; > + case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ > + ret = env->mmubpctrc; > + break; > + case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ > + ret = env->mmubpctrs; > + break; > + case 0x4c: /* SuperSPARC MMU Breakpoint Action */ > + ret = env->mmubpaction; > + break; > case 8: /* User code access, XXX */ > default: > do_unassigned_access(addr, 0, 0, asi, size); > @@ -2304,7 +2315,6 @@ void helper_st_asi(target_ulong addr, uint64_t > val, int asi, int size) > // descriptor diagnostic > case 0x36: /* I-cache flash clear */ > case 0x37: /* D-cache flash clear */ > - case 0x4c: /* breakpoint action */ > break; > case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ > { > @@ -2328,6 +2338,18 @@ void helper_st_asi(target_ulong addr, uint64_t > val, int asi, int size) > env->mmuregs[reg]); > } > break; > + case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ > + env->mmubpctrv = val& 0xffffffff; > + break; > + case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ > + env->mmubpctrc = val& 0x3; > + break; > + case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ > + env->mmubpctrs = val& 0x3; > + break; > + case 0x4c: /* SuperSPARC MMU Breakpoint Action */ > + env->mmubpaction = val& 0x1fff; > + break; > case 8: /* User code access, XXX */ > case 9: /* Supervisor code access, XXX */ > default: > The breakpoint action register is 64 bits wide.