[Qemu-devel] [PATCH 0/3] ppc: booke206: KVM MMU API and info tlb

[Qemu-devel] [PATCH 0/3] ppc: booke206: KVM MMU API and info tlb

[Scott Wood]

This depends on these qemu patches:
http://patchwork.ozlabs.org/patch/100826/
  (PPC: E500: Use MAS registers instead of internal TLB representation)
http://patchwork.ozlabs.org/patch/100821/
  (PPC: move TLBs to their own arrays)

For this functionality to work with KVM, this kernel patch is required:
http://www.spinics.net/lists/kvm-ppc/msg02843.html

Scott Wood (3):
  kvm: ppc: booke206: use MMU API
  ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages
  ppc: booke206: add "info tlb" support

 hmp-commands.hx        |    2 +-
 hw/ppce500_mpc8544ds.c |    4 ++-
 monitor.c              |    5 ++-
 target-ppc/cpu.h       |    8 +++-
 target-ppc/helper.c    |   94 ++++++++++++++++++++++++++++++++++++++++++++++-
 target-ppc/kvm.c       |   85 +++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 190 insertions(+), 8 deletions(-)

-- 
1.7.4.1

[Qemu-devel] [PATCH 1/3] kvm: ppc: booke206: use MMU API

[Scott Wood]

Share the TLB array with KVM.  This allows us to set the initial TLB
both on initial boot and reset, is useful for debugging, and could
eventually be used to support migration.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 hw/ppce500_mpc8544ds.c |    2 +
 target-ppc/cpu.h       |    2 +
 target-ppc/kvm.c       |   85 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 89 insertions(+), 0 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 5ac8843..3cdeb43 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -192,6 +192,8 @@ static void mmubooke_create_initial_mapping(CPUState *env,
     tlb->mas2 = va & TARGET_PAGE_MASK;
     tlb->mas7_3 = pa & TARGET_PAGE_MASK;
     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
+
+    env->tlb_dirty = true;
 }
 
 static void mpc8544ds_cpu_reset(void *opaque)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 46d86be..8191ed2 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -921,6 +921,8 @@ struct CPUPPCState {
     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
     /* 403 dedicated access protection registers */
     target_ulong pb[4];
+    bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
+    bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
 #endif
 
     /* Other registers */
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index e7b1b10..9a88fc9 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -122,6 +122,51 @@ static int kvm_arch_sync_sregs(CPUState *cenv)
     return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
 }
 
+static int kvm_booke206_tlb_init(CPUState *env)
+{
+#if defined(KVM_CAP_SW_TLB) && defined(KVM_MMU_FSL_BOOKE_NOHV)
+    struct kvm_book3e_206_tlb_params params = {};
+    struct kvm_config_tlb cfg = {};
+    size_t array_len;
+    unsigned int entries = 0;
+    int ret, i;
+
+    if (!kvm_enabled() ||
+        !kvm_check_extension(env->kvm_state, KVM_CAP_SW_TLB)) {
+        return 0;
+    }
+
+    for (i = 0; i < ARRAY_SIZE(params.tlb_sizes); i++) {
+        params.tlb_sizes[i] = booke206_tlb_size(env, i);
+        params.tlb_ways[i] = booke206_tlb_ways(env, i);
+        entries += params.tlb_sizes[i];
+    }
+
+    if (entries != env->nb_tlb) {
+        cpu_abort(env, "%s: nb_tlb mismatch\n", __func__);
+    }
+
+    array_len = sizeof(struct kvm_book3e_206_tlb_entry) * entries;
+    env->tlb_dirty = true;
+
+    cfg.array = (uintptr_t)env->tlb.tlbm;
+    cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
+    cfg.params = (uintptr_t)&params;
+    cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
+
+    ret = kvm_vcpu_ioctl(env, KVM_CONFIG_TLB, &cfg);
+    if (ret < 0) {
+        fprintf(stderr, "%s: couldn't KVM_CONFIG_TLB: %s\n",
+                __func__, strerror(-ret));
+        return ret;
+    }
+
+    env->kvm_sw_tlb = true;
+#endif
+
+    return 0;
+}
+
 int kvm_arch_init_vcpu(CPUState *cenv)
 {
     int ret;
@@ -133,6 +178,14 @@ int kvm_arch_init_vcpu(CPUState *cenv)
 
     idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv);
 
+    switch (cenv->mmu_model) {
+    case POWERPC_MMU_BOOKE206:
+        ret = kvm_booke206_tlb_init(cenv);
+        break;
+    default:
+        break;
+    }
+
     return ret;
 }
 
@@ -140,6 +193,33 @@ void kvm_arch_reset_vcpu(CPUState *env)
 {
 }
 
+static void kvm_sw_tlb_put(CPUState *env)
+{
+#if defined(KVM_CAP_SW_TLB)
+    struct kvm_dirty_tlb dirty_tlb;
+    unsigned char *bitmap;
+    int ret;
+
+    if (!env->kvm_sw_tlb) {
+        return;
+    }
+
+    bitmap = qemu_malloc((env->nb_tlb + 7) / 8);
+    memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
+
+    dirty_tlb.bitmap = (uintptr_t)bitmap;
+    dirty_tlb.num_dirty = env->nb_tlb;
+
+    ret = kvm_vcpu_ioctl(env, KVM_DIRTY_TLB, &dirty_tlb);
+    if (ret) {
+        fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
+                __func__, strerror(-ret));
+    }
+
+    qemu_free(bitmap);
+#endif
+}
+
 int kvm_arch_put_registers(CPUState *env, int level)
 {
     struct kvm_regs regs;
@@ -177,6 +257,11 @@ int kvm_arch_put_registers(CPUState *env, int level)
     if (ret < 0)
         return ret;
 
+    if (env->tlb_dirty) {
+        kvm_sw_tlb_put(env);
+        env->tlb_dirty = false;
+    }
+
     return ret;
 }
 
-- 
1.7.4.1

Re: [Qemu-devel] [PATCH 1/3] kvm: ppc: booke206: use MMU API

[Alexander Graf]

On 17.06.2011, at 22:39, Scott Wood wrote:

> Share the TLB array with KVM.  This allows us to set the initial TLB
> both on initial boot and reset, is useful for debugging, and could
> eventually be used to support migration.
> 
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> hw/ppce500_mpc8544ds.c |    2 +
> target-ppc/cpu.h       |    2 +
> target-ppc/kvm.c       |   85 ++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 89 insertions(+), 0 deletions(-)
> 
> diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
> index 5ac8843..3cdeb43 100644
> --- a/hw/ppce500_mpc8544ds.c
> +++ b/hw/ppce500_mpc8544ds.c
> @@ -192,6 +192,8 @@ static void mmubooke_create_initial_mapping(CPUState *env,
>     tlb->mas2 = va & TARGET_PAGE_MASK;
>     tlb->mas7_3 = pa & TARGET_PAGE_MASK;
>     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
> +
> +    env->tlb_dirty = true;
> }
> 
> static void mpc8544ds_cpu_reset(void *opaque)
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 46d86be..8191ed2 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -921,6 +921,8 @@ struct CPUPPCState {
>     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
>     /* 403 dedicated access protection registers */
>     target_ulong pb[4];
> +    bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
> +    bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
> #endif
> 
>     /* Other registers */
> diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
> index e7b1b10..9a88fc9 100644
> --- a/target-ppc/kvm.c
> +++ b/target-ppc/kvm.c
> @@ -122,6 +122,51 @@ static int kvm_arch_sync_sregs(CPUState *cenv)
>     return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
> }
> 
> +static int kvm_booke206_tlb_init(CPUState *env)
> +{
> +#if defined(KVM_CAP_SW_TLB) && defined(KVM_MMU_FSL_BOOKE_NOHV)

Those hopefully shouldn't be required anymore soon - when Jan's patches make it upstream. Jan, how's progress on that front?

> +    struct kvm_book3e_206_tlb_params params = {};

Hrm - I'm not familiar with that initialization. What exactly does it do? Set the struct contents to 0? Is this properly standardized? Usually, I see memset(0)s for that.

> +    struct kvm_config_tlb cfg = {};
> +    size_t array_len;
> +    unsigned int entries = 0;
> +    int ret, i;
> +
> +    if (!kvm_enabled() ||
> +        !kvm_check_extension(env->kvm_state, KVM_CAP_SW_TLB)) {
> +        return 0;
> +    }
> +
> +    for (i = 0; i < ARRAY_SIZE(params.tlb_sizes); i++) {

Please make this MAX(..., BOOKE206_MAX_TLBN) - I'd hope the compiler is clever enough to figure out we're dealing with a constant here and that way the code looks more secure (even though it's the same in practice).

Alternatively, you could just do an assert(... == BOOKE206_MAX_TLBN); before.

> +        params.tlb_sizes[i] = booke206_tlb_size(env, i);
> +        params.tlb_ways[i] = booke206_tlb_ways(env, i);
> +        entries += params.tlb_sizes[i];
> +    }
> +
> +    if (entries != env->nb_tlb) {
> +        cpu_abort(env, "%s: nb_tlb mismatch\n", __func__);
> +    }
> +

assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));

> +    array_len = sizeof(struct kvm_book3e_206_tlb_entry) * entries;
> +    env->tlb_dirty = true;
> +
> +    cfg.array = (uintptr_t)env->tlb.tlbm;
> +    cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
> +    cfg.params = (uintptr_t)&params;
> +    cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
> +
> +    ret = kvm_vcpu_ioctl(env, KVM_CONFIG_TLB, &cfg);
> +    if (ret < 0) {
> +        fprintf(stderr, "%s: couldn't KVM_CONFIG_TLB: %s\n",
> +                __func__, strerror(-ret));
> +        return ret;
> +    }
> +
> +    env->kvm_sw_tlb = true;
> +#endif
> +
> +    return 0;
> +}
> +
> int kvm_arch_init_vcpu(CPUState *cenv)
> {
>     int ret;
> @@ -133,6 +178,14 @@ int kvm_arch_init_vcpu(CPUState *cenv)
> 
>     idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv);
> 

Please add a comment here, explaining the occasional reader what we're doing here

> +    switch (cenv->mmu_model) {
> +    case POWERPC_MMU_BOOKE206:
> +        ret = kvm_booke206_tlb_init(cenv);
> +        break;
> +    default:
> +        break;
> +    }
> +
>     return ret;
> }
> 
> @@ -140,6 +193,33 @@ void kvm_arch_reset_vcpu(CPUState *env)
> {
> }
> 
> +static void kvm_sw_tlb_put(CPUState *env)
> +{
> +#if defined(KVM_CAP_SW_TLB)

See above

> +    struct kvm_dirty_tlb dirty_tlb;
> +    unsigned char *bitmap;
> +    int ret;
> +
> +    if (!env->kvm_sw_tlb) {
> +        return;
> +    }
> +
> +    bitmap = qemu_malloc((env->nb_tlb + 7) / 8);
> +    memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
> +
> +    dirty_tlb.bitmap = (uintptr_t)bitmap;
> +    dirty_tlb.num_dirty = env->nb_tlb;

Pretty simple for now, but I like the idea of starting simple :). Would it make sense to keep the bitmap allocated throughout the lifetime of env?


Alex

Re: [Qemu-devel] [PATCH 1/3] kvm: ppc: booke206: use MMU API

[Richard Henderson]

On 06/17/2011 04:28 PM, Alexander Graf wrote:
>> > +    struct kvm_book3e_206_tlb_params params = {};
> Hrm - I'm not familiar with that initialization. What exactly does it
> do? Set the struct contents to 0? Is this properly standardized?

Yes and yes.


r~

Re: [Qemu-devel] [PATCH 1/3] kvm: ppc: booke206: use MMU API

[Alexander Graf]

On 18.06.2011, at 18:13, Richard Henderson wrote:

> On 06/17/2011 04:28 PM, Alexander Graf wrote:
>>>> +    struct kvm_book3e_206_tlb_params params = {};
>> Hrm - I'm not familiar with that initialization. What exactly does it
>> do? Set the struct contents to 0? Is this properly standardized?
> 
> Yes and yes.

Ah, very nice. I wonder why I don't see it used more in code then :). Seems to be very handy to not clutter code with memset(0)s.


Alex

Re: [Qemu-devel] [PATCH 1/3] kvm: ppc: booke206: use MMU API

[Jan Kiszka]

On 2011-06-18 01:28, Alexander Graf wrote:
> 
> On 17.06.2011, at 22:39, Scott Wood wrote:
> 
>> Share the TLB array with KVM.  This allows us to set the initial TLB
>> both on initial boot and reset, is useful for debugging, and could
>> eventually be used to support migration.
>>
>> Signed-off-by: Scott Wood <scottwood@freescale.com>
>> ---
>> hw/ppce500_mpc8544ds.c |    2 +
>> target-ppc/cpu.h       |    2 +
>> target-ppc/kvm.c       |   85 ++++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 89 insertions(+), 0 deletions(-)
>>
>> diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
>> index 5ac8843..3cdeb43 100644
>> --- a/hw/ppce500_mpc8544ds.c
>> +++ b/hw/ppce500_mpc8544ds.c
>> @@ -192,6 +192,8 @@ static void mmubooke_create_initial_mapping(CPUState *env,
>>     tlb->mas2 = va & TARGET_PAGE_MASK;
>>     tlb->mas7_3 = pa & TARGET_PAGE_MASK;
>>     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
>> +
>> +    env->tlb_dirty = true;
>> }
>>
>> static void mpc8544ds_cpu_reset(void *opaque)
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 46d86be..8191ed2 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -921,6 +921,8 @@ struct CPUPPCState {
>>     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
>>     /* 403 dedicated access protection registers */
>>     target_ulong pb[4];
>> +    bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
>> +    bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
>> #endif
>>
>>     /* Other registers */
>> diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
>> index e7b1b10..9a88fc9 100644
>> --- a/target-ppc/kvm.c
>> +++ b/target-ppc/kvm.c
>> @@ -122,6 +122,51 @@ static int kvm_arch_sync_sregs(CPUState *cenv)
>>     return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
>> }
>>
>> +static int kvm_booke206_tlb_init(CPUState *env)
>> +{
>> +#if defined(KVM_CAP_SW_TLB) && defined(KVM_MMU_FSL_BOOKE_NOHV)
> 
> Those hopefully shouldn't be required anymore soon - when Jan's patches make it upstream. Jan, how's progress on that front?

I can only forward this question: Avi, what are the plans for
http://thread.gmane.org/gmane.comp.emulators.kvm.devel/73917?

Jan

-- 
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux

Re: [Qemu-devel] [PATCH 1/3] kvm: ppc: booke206: use MMU API

[Avi Kivity]

On 06/20/2011 10:41 AM, Jan Kiszka wrote:
>
> >  Those hopefully shouldn't be required anymore soon - when Jan's patches make it upstream. Jan, how's progress on that front?
>
> I can only forward this question: Avi, what are the plans for
> http://thread.gmane.org/gmane.comp.emulators.kvm.devel/73917?

Will apply once all comments are addressed.

-- 
error compiling committee.c: too many arguments to function

Re: [Qemu-devel] [PATCH 1/3] kvm: ppc: booke206: use MMU API

[Jan Kiszka]

On 2011-06-20 10:03, Avi Kivity wrote:
> On 06/20/2011 10:41 AM, Jan Kiszka wrote:
>>
>>>  Those hopefully shouldn't be required anymore soon - when Jan's patches make it upstream. Jan, how's progress on that front?
>>
>> I can only forward this question: Avi, what are the plans for
>> http://thread.gmane.org/gmane.comp.emulators.kvm.devel/73917?
> 
> Will apply once all comments are addressed.

Well, then go ahead :) - or did I miss a comment?

Jan

-- 
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux

Re: [Qemu-devel] [PATCH 1/3] kvm: ppc: booke206: use MMU API

[Avi Kivity]

On 06/20/2011 11:47 AM, Jan Kiszka wrote:
> On 2011-06-20 10:03, Avi Kivity wrote:
> >  On 06/20/2011 10:41 AM, Jan Kiszka wrote:
> >>
> >>>   Those hopefully shouldn't be required anymore soon - when Jan's patches make it upstream. Jan, how's progress on that front?
> >>
> >>  I can only forward this question: Avi, what are the plans for
> >>  http://thread.gmane.org/gmane.comp.emulators.kvm.devel/73917?
> >
> >  Will apply once all comments are addressed.
>
> Well, then go ahead :) - or did I miss a comment?

If everyone's happy I (or rather Marcelo this week) will be happy to apply.

-- 
error compiling committee.c: too many arguments to function

[Qemu-devel] [PATCH 2/3] ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages

[Scott Wood]

This definition is backward compatible with MAV=1.0 as long as
the guest does not set reserved bits in MAS1/MAS4.

Also, fix the shift in booke206_tlb_to_page_size -- it's the base
that should be able to hold a 4G page size, not the shift count.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
I ran into this when converting the info tlb patch to use the symbolic
MAS defines -- figured it would be better to add support for this element
of MAV=2.0 rather than remove it from "info tlb".

 hw/ppce500_mpc8544ds.c |    2 +-
 target-ppc/cpu.h       |    4 ++--
 target-ppc/helper.c    |    5 +++--
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 3cdeb43..a5e9378 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -177,7 +177,7 @@ out:
 /* Create -kernel TLB entries for BookE, linearly spanning 256MB.  */
 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
 {
-    return (ffs(size >> 10) - 1) >> 1;
+    return ffs(size >> 10) - 1;
 }
 
 static void mmubooke_create_initial_mapping(CPUState *env,
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8191ed2..5d80b1b 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -654,8 +654,8 @@ enum {
 #define MAS0_ATSEL_TLB     0
 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
 
-#define MAS1_TSIZE_SHIFT   8
-#define MAS1_TSIZE_MASK    (0xf << MAS1_TSIZE_SHIFT)
+#define MAS1_TSIZE_SHIFT   7
+#define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 
 #define MAS1_TS_SHIFT      12
 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 4e9b98a..5d007c5 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -1278,7 +1278,7 @@ target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb)
 {
     uint32_t tlbncfg;
     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
-    target_phys_addr_t tlbm_size;
+    int tlbm_size;
 
     tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
 
@@ -1286,9 +1286,10 @@ target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb)
         tlbm_size = (tlb->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
     } else {
         tlbm_size = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
+        tlbm_size <<= 1;
     }
 
-    return (1 << (tlbm_size << 1)) << 10;
+    return 1024ULL << tlbm_size;
 }
 
 /* TLB check function for MAS based SoftTLBs */
-- 
1.7.4.1

[Qemu-devel] [PATCH 3/3] ppc: booke206: add "info tlb" support

[Scott Wood]

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 hmp-commands.hx     |    2 +-
 monitor.c           |    5 ++-
 target-ppc/cpu.h    |    2 +
 target-ppc/helper.c |   89 +++++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 95 insertions(+), 3 deletions(-)

diff --git a/hmp-commands.hx b/hmp-commands.hx
index 6ad8806..014a4fb 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -1306,7 +1306,7 @@ show i8259 (PIC) state
 @item info pci
 show emulated PCI device info
 @item info tlb
-show virtual to physical memory mappings (i386, SH4 and SPARC only)
+show virtual to physical memory mappings (i386, SH4, SPARC, and PPC only)
 @item info mem
 show the active virtual memory mappings (i386 only)
 @item info jit
diff --git a/monitor.c b/monitor.c
index 6af6a4d..68e94af 100644
--- a/monitor.c
+++ b/monitor.c
@@ -2408,7 +2408,7 @@ static void tlb_info(Monitor *mon)
 
 #endif
 
-#if defined(TARGET_SPARC)
+#if defined(TARGET_SPARC) || defined(TARGET_PPC)
 static void tlb_info(Monitor *mon)
 {
     CPUState *env1 = mon_get_cpu();
@@ -2901,7 +2901,8 @@ static const mon_cmd_t info_cmds[] = {
         .user_print = do_pci_info_print,
         .mhandler.info_new = do_pci_info,
     },
-#if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC)
+#if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC) || \
+    defined(TARGET_PPC)
     {
         .name       = "tlb",
         .args_type  = "",
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 5d80b1b..48f7e2c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2020,4 +2020,6 @@ static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn,
 
 extern void (*cpu_ppc_hypercall)(CPUState *);
 
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
+
 #endif /* !defined (__CPU_PPC_H__) */
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 5d007c5..e22b1cb 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -1451,6 +1451,95 @@ found_tlb:
     return ret;
 }
 
+static const char *book3e_tsize_to_str[32] = {
+    "1K", "2K", "4K", "8K", "16K", "32K", "64K", "128K", "256K", "512K",
+    "1M", "2M", "4M", "8M", "16M", "32M", "64M", "128M", "256M", "512M",
+    "1G", "2G", "4G", "8G", "16G", "32G", "64G", "128G", "256G", "512G",
+    "1T", "2T"
+};
+
+static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
+                                     CPUState *env, int tlbn, int offset,
+                                     int tlbsize)
+{
+    ppcmas_tlb_t *entry;
+    int i;
+
+    cpu_fprintf(f, "\nTLB%d:\n", tlbn);
+    cpu_fprintf(f, "Effective          Physical           Size TID   TS SRWX URWX WIMGE U0123\n");
+
+    entry = &env->tlb.tlbm[offset];
+    for (i = 0; i < tlbsize; i++, entry++) {
+        target_phys_addr_t ea, pa, size;
+        int tsize;
+
+        /* valid? */
+        if (!(entry->mas1 & MAS1_VALID)) {
+            continue;
+        }
+
+        tsize = (entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
+        size = 1024ULL << tsize;
+        ea = entry->mas2 & ~(size - 1);
+        pa = entry->mas7_3 & ~(size - 1);
+
+        cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u  S%c%c%c U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
+                    (uint64_t)ea, (uint64_t)pa,
+                    book3e_tsize_to_str[tsize],
+                    (entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT,
+                    (entry->mas1 & MAS1_TS) >> MAS1_TS_SHIFT,
+                    entry->mas7_3 & MAS3_SR ? 'R' : '-',
+                    entry->mas7_3 & MAS3_SW ? 'W' : '-',
+                    entry->mas7_3 & MAS3_SX ? 'X' : '-',
+                    entry->mas7_3 & MAS3_UR ? 'R' : '-',
+                    entry->mas7_3 & MAS3_UW ? 'W' : '-',
+                    entry->mas7_3 & MAS3_UX ? 'X' : '-',
+                    entry->mas2 & MAS2_W ? 'W' : '-',
+                    entry->mas2 & MAS2_I ? 'I' : '-',
+                    entry->mas2 & MAS2_M ? 'M' : '-',
+                    entry->mas2 & MAS2_G ? 'G' : '-',
+                    entry->mas2 & MAS2_E ? 'E' : '-',
+                    entry->mas7_3 & MAS3_U0 ? '0' : '-',
+                    entry->mas7_3 & MAS3_U1 ? '1' : '-',
+                    entry->mas7_3 & MAS3_U2 ? '2' : '-',
+                    entry->mas7_3 & MAS3_U3 ? '3' : '-');
+    }
+}
+
+static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
+                                 CPUState *env)
+{
+    int offset = 0;
+    int i;
+
+    if (kvm_enabled() && !env->kvm_sw_tlb) {
+        cpu_fprintf(f, "Cannot access KVM TLB\n");
+        return;
+    }
+
+    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
+        int size = booke206_tlb_size(env, i);
+
+        if (size == 0) {
+            continue;
+        }
+
+        mmubooke206_dump_one_tlb(f, cpu_fprintf, env, i, offset, size);
+        offset += size;
+    }
+}
+
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
+{
+    switch (env->mmu_model) {
+    case POWERPC_MMU_BOOKE206:
+        mmubooke206_dump_mmu(f, cpu_fprintf, env);
+        break;
+    default:
+        cpu_fprintf(f, "%s: unimplemented\n", __func__);
+    }
+}
+
 static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
                                  target_ulong eaddr, int rw)
 {
-- 
1.7.4.1

Re: [Qemu-devel] [PATCH 3/3] ppc: booke206: add "info tlb" support

[Alexander Graf]

On 17.06.2011, at 22:39, Scott Wood wrote:

> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> hmp-commands.hx     |    2 +-
> monitor.c           |    5 ++-
> target-ppc/cpu.h    |    2 +
> target-ppc/helper.c |   89 +++++++++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 95 insertions(+), 3 deletions(-)
> 
> diff --git a/hmp-commands.hx b/hmp-commands.hx
> index 6ad8806..014a4fb 100644
> --- a/hmp-commands.hx
> +++ b/hmp-commands.hx
> @@ -1306,7 +1306,7 @@ show i8259 (PIC) state
> @item info pci
> show emulated PCI device info
> @item info tlb
> -show virtual to physical memory mappings (i386, SH4 and SPARC only)
> +show virtual to physical memory mappings (i386, SH4, SPARC, and PPC only)
> @item info mem
> show the active virtual memory mappings (i386 only)
> @item info jit
> diff --git a/monitor.c b/monitor.c
> index 6af6a4d..68e94af 100644
> --- a/monitor.c
> +++ b/monitor.c
> @@ -2408,7 +2408,7 @@ static void tlb_info(Monitor *mon)
> 
> #endif
> 
> -#if defined(TARGET_SPARC)
> +#if defined(TARGET_SPARC) || defined(TARGET_PPC)
> static void tlb_info(Monitor *mon)
> {
>     CPUState *env1 = mon_get_cpu();
> @@ -2901,7 +2901,8 @@ static const mon_cmd_t info_cmds[] = {
>         .user_print = do_pci_info_print,
>         .mhandler.info_new = do_pci_info,
>     },
> -#if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC)
> +#if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC) || \
> +    defined(TARGET_PPC)
>     {
>         .name       = "tlb",
>         .args_type  = "",
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 5d80b1b..48f7e2c 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -2020,4 +2020,6 @@ static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn,
> 
> extern void (*cpu_ppc_hypercall)(CPUState *);
> 
> +void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
> +
> #endif /* !defined (__CPU_PPC_H__) */
> diff --git a/target-ppc/helper.c b/target-ppc/helper.c
> index 5d007c5..e22b1cb 100644
> --- a/target-ppc/helper.c
> +++ b/target-ppc/helper.c
> @@ -1451,6 +1451,95 @@ found_tlb:
>     return ret;
> }
> 
> +static const char *book3e_tsize_to_str[32] = {
> +    "1K", "2K", "4K", "8K", "16K", "32K", "64K", "128K", "256K", "512K",
> +    "1M", "2M", "4M", "8M", "16M", "32M", "64M", "128M", "256M", "512M",
> +    "1G", "2G", "4G", "8G", "16G", "32G", "64G", "128G", "256G", "512G",
> +    "1T", "2T"
> +};
> +
> +static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
> +                                     CPUState *env, int tlbn, int offset,
> +                                     int tlbsize)
> +{
> +    ppcmas_tlb_t *entry;
> +    int i;
> +
> +    cpu_fprintf(f, "\nTLB%d:\n", tlbn);
> +    cpu_fprintf(f, "Effective          Physical           Size TID   TS SRWX URWX WIMGE U0123\n");
> +
> +    entry = &env->tlb.tlbm[offset];
> +    for (i = 0; i < tlbsize; i++, entry++) {
> +        target_phys_addr_t ea, pa, size;
> +        int tsize;
> +
> +        /* valid? */
> +        if (!(entry->mas1 & MAS1_VALID)) {
> +            continue;
> +        }
> +
> +        tsize = (entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
> +        size = 1024ULL << tsize;

Isn't that what booke206_tlb_to_page_size() is there for? Hrm - but you still need tsize. I see. Fair enough - I can't think of a cleaner way atm either.


Alex

Re: [Qemu-devel] [PATCH 0/3] ppc: booke206: KVM MMU API and info tlb

[Alexander Graf]

On 17.06.2011, at 22:38, Scott Wood wrote:

> This depends on these qemu patches:
> http://patchwork.ozlabs.org/patch/100826/
>  (PPC: E500: Use MAS registers instead of internal TLB representation)
> http://patchwork.ozlabs.org/patch/100821/
>  (PPC: move TLBs to their own arrays)
> 
> For this functionality to work with KVM, this kernel patch is required:
> http://www.spinics.net/lists/kvm-ppc/msg02843.html

Could you please resend without the #ifdefs? Jan's patches that get rid of the host kernel header dependencies finally got merged :). Please also execute his header update script in scripts/ with the MMU API patch applied.


Alex

Re: [Qemu-devel] [PATCH 0/3] ppc: booke206: KVM MMU API and info tlb

[Scott Wood]

On Wed, 6 Jul 2011 18:38:04 +0200
Alexander Graf <agraf@suse.de> wrote:

> 
> On 17.06.2011, at 22:38, Scott Wood wrote:
> 
> > This depends on these qemu patches:
> > http://patchwork.ozlabs.org/patch/100826/
> >  (PPC: E500: Use MAS registers instead of internal TLB representation)
> > http://patchwork.ozlabs.org/patch/100821/
> >  (PPC: move TLBs to their own arrays)
> > 
> > For this functionality to work with KVM, this kernel patch is required:
> > http://www.spinics.net/lists/kvm-ppc/msg02843.html
> 
> Could you please resend without the #ifdefs? Jan's patches that get rid of the host kernel header dependencies finally got merged :). Please also execute his header update script in scripts/ with the MMU API patch applied.

Yes, I'll try to respin today.

-Scott

Re: [Qemu-devel] [PATCH 0/3] ppc: booke206: KVM MMU API and info tlb

[Scott Wood]

On Wed, 6 Jul 2011 11:45:47 -0500
Scott Wood <scottwood@freescale.com> wrote:

> On Wed, 6 Jul 2011 18:38:04 +0200
> Alexander Graf <agraf@suse.de> wrote:
> 
> > 
> > On 17.06.2011, at 22:38, Scott Wood wrote:
> > 
> > > This depends on these qemu patches:
> > > http://patchwork.ozlabs.org/patch/100826/
> > >  (PPC: E500: Use MAS registers instead of internal TLB representation)
> > > http://patchwork.ozlabs.org/patch/100821/
> > >  (PPC: move TLBs to their own arrays)
> > > 
> > > For this functionality to work with KVM, this kernel patch is required:
> > > http://www.spinics.net/lists/kvm-ppc/msg02843.html
> > 
> > Could you please resend without the #ifdefs? Jan's patches that get rid of the host kernel header dependencies finally got merged :). Please also execute his header update script in scripts/ with the MMU API patch applied.
> 
> Yes, I'll try to respin today.

I got bogged down trying to fix some issues on the kernel side, relating to
page reference tracking, that will get worse when qemu can change the
geometry.  Don't apply the current kernel patch.  I'll have respins of both
the kernel and qemu patches soon -- but not today. :-)

-Scott