From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42598) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QlKsk-0000td-Pg for qemu-devel@nongnu.org; Mon, 25 Jul 2011 09:07:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QlKsj-0006Yn-Md for qemu-devel@nongnu.org; Mon, 25 Jul 2011 09:07:38 -0400 Received: from mail-yi0-f45.google.com ([209.85.218.45]:36779) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QlKsj-0006Yb-J7 for qemu-devel@nongnu.org; Mon, 25 Jul 2011 09:07:37 -0400 Received: by yia25 with SMTP id 25so2627980yia.4 for ; Mon, 25 Jul 2011 06:07:36 -0700 (PDT) Message-ID: <4E2D6A97.9050606@codemonkey.ws> Date: Mon, 25 Jul 2011 08:07:35 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <1311180636-17012-1-git-send-email-avi@redhat.com> <1311180636-17012-87-git-send-email-avi@redhat.com> In-Reply-To: <1311180636-17012-87-git-send-email-avi@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC v5 86/86] 440fx: fix PAM, PCI holes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org On 07/20/2011 11:50 AM, Avi Kivity wrote: > The current implementation of PAM and the PCI holes is broken in several > ways: > > - PCI BARs are not restricted to the PCI hole (a BAR may hide memory) Technically, a BAR can be mapped to any non-RAM memory location. > - PCI devices do not respect PAM (if a PCI device maps a region while > PAM maps the region to RAM, the request will be honored) I assume you mean SMM shadowing, right? PAM doesn't cover an area that's ever forwarded to the PCI bus. > This patch fixes things by introducing a pci address space, and using > memory region aliases to represent PAM regions, SMRAM, and PCI holes. > > The memory hierarchy looks something like > > system_memory > | > +--- low memory alias (0-0xe0000000) According to the spec, PCI memory doesn't start at e00... but rather at the top of RAM. In fact, this is what the spec says: "The address range from the top of main DRAM to 4 Gbytes (top of physical memory space supported by the 440FX PCIset) is normally mapped to PCI. The PMC forwards all accesses within this address range to PCI. There are two sub-ranges within this address range defined as APIC Configuration Space and High BIOS Address Range." So the right thing to do is to forward all accesses from low_memory_memsize ... 4GB to the PCI bus. Regards, Anthony Liguori