From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:56683) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QoVNY-0008UQ-Aw for qemu-devel@nongnu.org; Wed, 03 Aug 2011 02:56:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QoVNX-0005Zb-Dz for qemu-devel@nongnu.org; Wed, 03 Aug 2011 02:56:32 -0400 Received: from mx1.redhat.com ([209.132.183.28]:27763) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QoVNX-0005ZX-3j for qemu-devel@nongnu.org; Wed, 03 Aug 2011 02:56:31 -0400 Message-ID: <4E38F118.7060602@redhat.com> Date: Wed, 03 Aug 2011 09:56:24 +0300 From: Avi Kivity MIME-Version: 1.0 References: <4E381EA7.2070809@redhat.com> <4E383CE5.4010405@siemens.com> <4E3866DA.2050608@codemonkey.ws> <4E386C44.607@redhat.com> <4E38B37F.8010100@codemonkey.ws> In-Reply-To: <4E38B37F.8010100@codemonkey.ws> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] modelling omap_gpmc with the hierarchical memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Jan Kiszka , QEMU Developers , Peter Maydell On 08/03/2011 05:33 AM, Anthony Liguori wrote: > On 08/02/2011 04:29 PM, Avi Kivity wrote: >> On 08/03/2011 12:06 AM, Anthony Liguori wrote: >>> >>> The qdev level should be the common base that makes sense for *all* >>> qdev devices. IRQ management does not belong in DeviceState because >>> what you do for a simple LCD is not what you do for an MSI-X capable >>> PCI device. >>> >>> This is what QOM properties tries to address. It should be possible to >>> create a simple device, and register plugs/sockets for GPIO pins >>> without pushing GPIO knowledge into the base class. >>> >>> In a QDev world, the right approach is to have a GpioDevice base class >>> that implements this sort of logic for devices where it makes sense. >>> That's what SysBusDevice sort of wants to be but it somehow ended up >>> as yet another base class for everything. >>> >> >> Doesn't this end up requiring multiple inheritance, and a ton of >> boilerplate in addition? > > I don't see a ton of boiler plate nor do I see multiple inheritance. > Either you have devices that live on a bus that interact with other > devices via the bus interface or you have devices that interact > through Pin interactions. If you have a GpioDevice to for devices/buses with gpio and a FooDevice for devices/buses with foo, how do you do a device that has both gpio and foo? > > But pushing everything into qdev is wrong. This is a classic trap > with object oriented modelling. Inheritance is supposed to model is-a > relationships, not "may-implement in some subclasses". Not only does > it cause unnecessary bloat, it causes brittleness. > > What in the world would DeviceState::num_gpio_out mean for a PCI device? Nothing. It's always zero. > It doesn't make sense at all which means it doesn't belong in > DeviceState. What if the common subset is empty? > Unless we're modelling the pin inputs and outputs for every device > that we possibly support.. But we're in for a world of hurt if that's > what our goals are. Connecting PCI devices to their busses will be, > interesting, to say the least :-) We use the high level functions to model address/data/irq/decode/etc. and gpio for the stuff that falls between the chairs. -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.