From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44790) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QpL15-0005uS-Ak for qemu-devel@nongnu.org; Fri, 05 Aug 2011 10:04:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QpL14-0003fp-DQ for qemu-devel@nongnu.org; Fri, 05 Aug 2011 10:04:47 -0400 Received: from mail-pz0-f42.google.com ([209.85.210.42]:38540) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QpL14-0003fc-6U for qemu-devel@nongnu.org; Fri, 05 Aug 2011 10:04:46 -0400 Received: by pzk37 with SMTP id 37so4673640pzk.29 for ; Fri, 05 Aug 2011 07:04:45 -0700 (PDT) Message-ID: <4E3BF879.5060004@codemonkey.ws> Date: Fri, 05 Aug 2011 09:04:41 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <1312463195-13605-1-git-send-email-avi@redhat.com> <1312463195-13605-6-git-send-email-avi@redhat.com> In-Reply-To: <1312463195-13605-6-git-send-email-avi@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 05/39] cirrus: simplify mmio BAR access functions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, "Michael S. Tsirkin" On 08/04/2011 08:06 AM, Avi Kivity wrote: > Make use of the memory API's ability to satisfy multi-byte accesses via > multiple single-byte accesses. > > Reviewed-by: Richard Henderson > Signed-off-by: Avi Kivity > --- > hw/cirrus_vga.c | 78 +++++------------------------------------------------- > 1 files changed, 8 insertions(+), 70 deletions(-) > > diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c > index d1475dd..6e1aa75 100644 > --- a/hw/cirrus_vga.c > +++ b/hw/cirrus_vga.c > @@ -2828,12 +2828,11 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) > * > ***************************************/ > > -static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) > +static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr, > + unsigned size) > { > CirrusVGAState *s = opaque; > > - addr&= CIRRUS_PNPMMIO_SIZE - 1; > - > if (addr>= 0x100) { > return cirrus_mmio_blt_read(s, addr - 0x100); > } else { > @@ -2841,33 +2840,11 @@ static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) > } > } > > -static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) > -{ > - uint32_t v; > - > - v = cirrus_mmio_readb(opaque, addr); > - v |= cirrus_mmio_readb(opaque, addr + 1)<< 8; > - return v; > -} > - > -static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) > -{ > - uint32_t v; > - > - v = cirrus_mmio_readb(opaque, addr); > - v |= cirrus_mmio_readb(opaque, addr + 1)<< 8; > - v |= cirrus_mmio_readb(opaque, addr + 2)<< 16; > - v |= cirrus_mmio_readb(opaque, addr + 3)<< 24; > - return v; > -} > - > -static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, > - uint32_t val) > +static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr, > + uint64_t val, unsigned size) > { > CirrusVGAState *s = opaque; > > - addr&= CIRRUS_PNPMMIO_SIZE - 1; > - > if (addr>= 0x100) { > cirrus_mmio_blt_write(s, addr - 0x100, val); > } else { > @@ -2875,53 +2852,14 @@ static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, > } > } > > -static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, > - uint32_t val) > -{ > - cirrus_mmio_writeb(opaque, addr, val& 0xff); > - cirrus_mmio_writeb(opaque, addr + 1, (val>> 8)& 0xff); > -} > - > -static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, > - uint32_t val) > -{ > - cirrus_mmio_writeb(opaque, addr, val& 0xff); > - cirrus_mmio_writeb(opaque, addr + 1, (val>> 8)& 0xff); > - cirrus_mmio_writeb(opaque, addr + 2, (val>> 16)& 0xff); > - cirrus_mmio_writeb(opaque, addr + 3, (val>> 24)& 0xff); > -} > - > - > -static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr, > - unsigned size) > -{ > - CirrusVGAState *s = opaque; > - > - switch (size) { > - case 1: return cirrus_mmio_readb(s, addr); > - case 2: return cirrus_mmio_readw(s, addr); > - case 4: return cirrus_mmio_readl(s, addr); > - default: abort(); > - } > -}; > - > -static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr, > - uint64_t data, unsigned size) > -{ > - CirrusVGAState *s = opaque; > - > - switch (size) { > - case 1: return cirrus_mmio_writeb(s, addr, data); > - case 2: return cirrus_mmio_writew(s, addr, data); > - case 4: return cirrus_mmio_writel(s, addr, data); > - default: abort(); > - } > -}; > - > static const MemoryRegionOps cirrus_mmio_io_ops = { > .read = cirrus_mmio_read, > .write = cirrus_mmio_write, > .endianness = DEVICE_LITTLE_ENDIAN, > + .impl = { > + .min_access_size = 1, > + .max_access_size = 1, > + }, > }; old_mmio? Regards, Anthony Liguori > /* load/save state */