* [Qemu-devel] [PATCH V2] Memory API conversion for mpic (openpic.c)
@ 2011-08-30 15:46 Fabien Chouteau
2011-08-31 9:16 ` Avi Kivity
0 siblings, 1 reply; 6+ messages in thread
From: Fabien Chouteau @ 2011-08-30 15:46 UTC (permalink / raw)
To: qemu-devel; +Cc: avi
This patch converts mpic to the new memory API (through old mmio).
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
hw/openpic.c | 207 ++++++++++++++++++++++++++----------------------
hw/openpic.h | 4 +-
hw/ppce500_mpc8544ds.c | 2 +-
3 files changed, 114 insertions(+), 99 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 26c96e2..88e997e 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -206,6 +206,10 @@ typedef struct IRQ_dst_t {
typedef struct openpic_t {
PCIDevice pci_dev;
MemoryRegion mem;
+
+ /* Sub-regions */
+ MemoryRegion sub_io_mem[7];
+
/* Global registers */
uint32_t frep; /* Feature reporting register */
uint32_t glbc; /* Global configuration register */
@@ -1537,107 +1541,122 @@ static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
return retval;
}
-static CPUWriteMemoryFunc * const mpic_glb_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &openpic_gbl_write,
-};
-
-static CPUReadMemoryFunc * const mpic_glb_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &openpic_gbl_read,
-};
-
-static CPUWriteMemoryFunc * const mpic_tmr_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_timer_write,
+static const MemoryRegionOps mpic_glb_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ openpic_gbl_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ openpic_gbl_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUReadMemoryFunc * const mpic_tmr_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_timer_read,
+static const MemoryRegionOps mpic_tmr_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_timer_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_timer_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUWriteMemoryFunc * const mpic_cpu_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &openpic_cpu_write,
+static const MemoryRegionOps mpic_cpu_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ openpic_cpu_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ openpic_cpu_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUReadMemoryFunc * const mpic_cpu_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &openpic_cpu_read,
+static const MemoryRegionOps mpic_ext_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_src_ext_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_src_ext_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUWriteMemoryFunc * const mpic_ext_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_src_ext_write,
+static const MemoryRegionOps mpic_int_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_src_int_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_src_int_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUReadMemoryFunc * const mpic_ext_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_src_ext_read,
+static const MemoryRegionOps mpic_msg_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_src_msg_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_src_msg_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUWriteMemoryFunc * const mpic_int_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_src_int_write,
+static const MemoryRegionOps mpic_msi_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_src_msi_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_src_msi_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUReadMemoryFunc * const mpic_int_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_src_int_read,
-};
-
-static CPUWriteMemoryFunc * const mpic_msg_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_src_msg_write,
-};
-
-static CPUReadMemoryFunc * const mpic_msg_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_src_msg_read,
-};
-static CPUWriteMemoryFunc * const mpic_msi_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_src_msi_write,
-};
-
-static CPUReadMemoryFunc * const mpic_msi_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_src_msi_read,
-};
-
-qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
- qemu_irq **irqs, qemu_irq irq_out)
+qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+ int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
{
- openpic_t *mpp;
- int i;
+ openpic_t *mpp;
+ int i;
struct {
- CPUReadMemoryFunc * const *read;
- CPUWriteMemoryFunc * const *write;
- target_phys_addr_t start_addr;
- ram_addr_t size;
+ const char *name;
+ MemoryRegionOps const *ops;
+ target_phys_addr_t start_addr;
+ ram_addr_t size;
} const list[] = {
- {mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
- {mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
- {mpic_ext_read, mpic_ext_write, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
- {mpic_int_read, mpic_int_write, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
- {mpic_msg_read, mpic_msg_write, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
- {mpic_msi_read, mpic_msi_write, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
- {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
+ {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
+ {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
+ {"ext", &mpic_ext_ops, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
+ {"int", &mpic_int_ops, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
+ {"msg", &mpic_msg_ops, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
+ {"msi", &mpic_msi_ops, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
+ {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
};
/* XXX: for now, only one CPU is supported */
@@ -1646,16 +1665,16 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
mpp = g_malloc0(sizeof(openpic_t));
+ memory_region_init(&mpp->mem, "mpic", 0x40000);
+ memory_region_add_subregion(address_space, base, &mpp->mem);
+
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
- int mem_index;
- mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
- DEVICE_BIG_ENDIAN);
- if (mem_index < 0) {
- goto free;
- }
- cpu_register_physical_memory(base + list[i].start_addr,
- list[i].size, mem_index);
+ memory_region_init_io(&mpp->sub_io_mem[i], list[i].ops, mpp,
+ list[i].name, list[i].size);
+
+ memory_region_add_subregion(&mpp->mem, list[i].start_addr,
+ &mpp->sub_io_mem[i]);
}
mpp->nb_cpus = nb_cpus;
@@ -1674,8 +1693,4 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
qemu_register_reset(mpic_reset, mpp);
return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
-
-free:
- g_free(mpp);
- return NULL;
}
diff --git a/hw/openpic.h b/hw/openpic.h
index 75de361..715f084 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -13,6 +13,6 @@ enum {
qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
-qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
- qemu_irq **irqs, qemu_irq irq_out);
+qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+ int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
#endif /* __OPENPIC_H__ */
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 274b37c..28acf0b 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -272,7 +272,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
irqs = g_malloc0(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT];
irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT];
- mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
+ mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
/* Serial */
if (serial_hds[0]) {
--
1.7.4.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [Qemu-devel] [PATCH V2] Memory API conversion for mpic (openpic.c)
2011-08-30 15:46 [Qemu-devel] [PATCH V2] Memory API conversion for mpic (openpic.c) Fabien Chouteau
@ 2011-08-31 9:16 ` Avi Kivity
2011-08-31 9:22 ` Fabien Chouteau
0 siblings, 1 reply; 6+ messages in thread
From: Avi Kivity @ 2011-08-31 9:16 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: qemu-devel
On 08/30/2011 06:46 PM, Fabien Chouteau wrote:
> This patch converts mpic to the new memory API (through old mmio).
I got two copies of this, which one is the right one?
This one looks good.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH V2] Memory API conversion for mpic (openpic.c)
2011-08-31 9:16 ` Avi Kivity
@ 2011-08-31 9:22 ` Fabien Chouteau
2011-08-31 9:35 ` Avi Kivity
0 siblings, 1 reply; 6+ messages in thread
From: Fabien Chouteau @ 2011-08-31 9:22 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel
On 31/08/2011 11:16, Avi Kivity wrote:
> On 08/30/2011 06:46 PM, Fabien Chouteau wrote:
>> This patch converts mpic to the new memory API (through old mmio).
>
> I got two copies of this, which one is the right one?
Excuse me, I sent the same patch twice...
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH V2] Memory API conversion for mpic (openpic.c)
2011-08-31 9:22 ` Fabien Chouteau
@ 2011-08-31 9:35 ` Avi Kivity
2011-08-31 9:37 ` Fabien Chouteau
0 siblings, 1 reply; 6+ messages in thread
From: Avi Kivity @ 2011-08-31 9:35 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: qemu-devel
On 08/31/2011 12:22 PM, Fabien Chouteau wrote:
> On 31/08/2011 11:16, Avi Kivity wrote:
> > On 08/30/2011 06:46 PM, Fabien Chouteau wrote:
> >> This patch converts mpic to the new memory API (through old mmio).
> >
> > I got two copies of this, which one is the right one?
>
> Excuse me, I sent the same patch twice...
>
No problem, added to memory/queue, thanks.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH V2] Memory API conversion for mpic (openpic.c)
2011-08-31 9:35 ` Avi Kivity
@ 2011-08-31 9:37 ` Fabien Chouteau
0 siblings, 0 replies; 6+ messages in thread
From: Fabien Chouteau @ 2011-08-31 9:37 UTC (permalink / raw)
To: Avi Kivity; +Cc: qemu-devel
On 31/08/2011 11:35, Avi Kivity wrote:
> On 08/31/2011 12:22 PM, Fabien Chouteau wrote:
>> On 31/08/2011 11:16, Avi Kivity wrote:
>> > On 08/30/2011 06:46 PM, Fabien Chouteau wrote:
>> >> This patch converts mpic to the new memory API (through old mmio).
>> >
>> > I got two copies of this, which one is the right one?
>>
>> Excuse me, I sent the same patch twice...
>>
>
> No problem, added to memory/queue, thanks.
>
Great!
thank you,
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH V2] Memory API conversion for mpic (openpic.c)
@ 2011-08-30 15:44 Fabien Chouteau
0 siblings, 0 replies; 6+ messages in thread
From: Fabien Chouteau @ 2011-08-30 15:44 UTC (permalink / raw)
To: qemu-devel; +Cc: avi
This patch converts mpic to the new memory API (through old mmio).
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
hw/openpic.c | 207 ++++++++++++++++++++++++++----------------------
hw/openpic.h | 4 +-
hw/ppce500_mpc8544ds.c | 2 +-
3 files changed, 114 insertions(+), 99 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 26c96e2..88e997e 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -206,6 +206,10 @@ typedef struct IRQ_dst_t {
typedef struct openpic_t {
PCIDevice pci_dev;
MemoryRegion mem;
+
+ /* Sub-regions */
+ MemoryRegion sub_io_mem[7];
+
/* Global registers */
uint32_t frep; /* Feature reporting register */
uint32_t glbc; /* Global configuration register */
@@ -1537,107 +1541,122 @@ static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
return retval;
}
-static CPUWriteMemoryFunc * const mpic_glb_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &openpic_gbl_write,
-};
-
-static CPUReadMemoryFunc * const mpic_glb_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &openpic_gbl_read,
-};
-
-static CPUWriteMemoryFunc * const mpic_tmr_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_timer_write,
+static const MemoryRegionOps mpic_glb_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ openpic_gbl_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ openpic_gbl_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUReadMemoryFunc * const mpic_tmr_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_timer_read,
+static const MemoryRegionOps mpic_tmr_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_timer_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_timer_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUWriteMemoryFunc * const mpic_cpu_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &openpic_cpu_write,
+static const MemoryRegionOps mpic_cpu_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ openpic_cpu_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ openpic_cpu_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUReadMemoryFunc * const mpic_cpu_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &openpic_cpu_read,
+static const MemoryRegionOps mpic_ext_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_src_ext_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_src_ext_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUWriteMemoryFunc * const mpic_ext_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_src_ext_write,
+static const MemoryRegionOps mpic_int_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_src_int_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_src_int_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUReadMemoryFunc * const mpic_ext_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_src_ext_read,
+static const MemoryRegionOps mpic_msg_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_src_msg_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_src_msg_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUWriteMemoryFunc * const mpic_int_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_src_int_write,
+static const MemoryRegionOps mpic_msi_ops = {
+ .old_mmio = {
+ .write = { openpic_buggy_write,
+ openpic_buggy_write,
+ mpic_src_msi_write,
+ },
+ .read = { openpic_buggy_read,
+ openpic_buggy_read,
+ mpic_src_msi_read,
+ },
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUReadMemoryFunc * const mpic_int_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_src_int_read,
-};
-
-static CPUWriteMemoryFunc * const mpic_msg_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_src_msg_write,
-};
-
-static CPUReadMemoryFunc * const mpic_msg_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_src_msg_read,
-};
-static CPUWriteMemoryFunc * const mpic_msi_write[] = {
- &openpic_buggy_write,
- &openpic_buggy_write,
- &mpic_src_msi_write,
-};
-
-static CPUReadMemoryFunc * const mpic_msi_read[] = {
- &openpic_buggy_read,
- &openpic_buggy_read,
- &mpic_src_msi_read,
-};
-
-qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
- qemu_irq **irqs, qemu_irq irq_out)
+qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+ int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
{
- openpic_t *mpp;
- int i;
+ openpic_t *mpp;
+ int i;
struct {
- CPUReadMemoryFunc * const *read;
- CPUWriteMemoryFunc * const *write;
- target_phys_addr_t start_addr;
- ram_addr_t size;
+ const char *name;
+ MemoryRegionOps const *ops;
+ target_phys_addr_t start_addr;
+ ram_addr_t size;
} const list[] = {
- {mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
- {mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
- {mpic_ext_read, mpic_ext_write, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
- {mpic_int_read, mpic_int_write, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
- {mpic_msg_read, mpic_msg_write, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
- {mpic_msi_read, mpic_msi_write, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
- {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
+ {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
+ {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
+ {"ext", &mpic_ext_ops, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
+ {"int", &mpic_int_ops, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
+ {"msg", &mpic_msg_ops, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
+ {"msi", &mpic_msi_ops, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
+ {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
};
/* XXX: for now, only one CPU is supported */
@@ -1646,16 +1665,16 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
mpp = g_malloc0(sizeof(openpic_t));
+ memory_region_init(&mpp->mem, "mpic", 0x40000);
+ memory_region_add_subregion(address_space, base, &mpp->mem);
+
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
- int mem_index;
- mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
- DEVICE_BIG_ENDIAN);
- if (mem_index < 0) {
- goto free;
- }
- cpu_register_physical_memory(base + list[i].start_addr,
- list[i].size, mem_index);
+ memory_region_init_io(&mpp->sub_io_mem[i], list[i].ops, mpp,
+ list[i].name, list[i].size);
+
+ memory_region_add_subregion(&mpp->mem, list[i].start_addr,
+ &mpp->sub_io_mem[i]);
}
mpp->nb_cpus = nb_cpus;
@@ -1674,8 +1693,4 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
qemu_register_reset(mpic_reset, mpp);
return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
-
-free:
- g_free(mpp);
- return NULL;
}
diff --git a/hw/openpic.h b/hw/openpic.h
index 75de361..715f084 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -13,6 +13,6 @@ enum {
qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
-qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
- qemu_irq **irqs, qemu_irq irq_out);
+qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+ int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
#endif /* __OPENPIC_H__ */
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 274b37c..28acf0b 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -272,7 +272,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
irqs = g_malloc0(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT];
irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT];
- mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
+ mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
/* Serial */
if (serial_hds[0]) {
--
1.7.4.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2011-08-31 9:37 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-08-30 15:46 [Qemu-devel] [PATCH V2] Memory API conversion for mpic (openpic.c) Fabien Chouteau
2011-08-31 9:16 ` Avi Kivity
2011-08-31 9:22 ` Fabien Chouteau
2011-08-31 9:35 ` Avi Kivity
2011-08-31 9:37 ` Fabien Chouteau
-- strict thread matches above, loose matches on Subject: below --
2011-08-30 15:44 Fabien Chouteau
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