From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:37765) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qz8ii-0003fh-T5 for qemu-devel@nongnu.org; Thu, 01 Sep 2011 10:58:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qz8ih-0001A5-Ee for qemu-devel@nongnu.org; Thu, 01 Sep 2011 10:58:20 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44115 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qz8ih-00017z-1N for qemu-devel@nongnu.org; Thu, 01 Sep 2011 10:58:19 -0400 Message-ID: <4E5F9D83.10108@suse.de> Date: Thu, 01 Sep 2011 16:58:11 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1314436348-28837-1-git-send-email-daniel@drv.nu> <2803ABD2-E8EA-4AE3-9AD1-21FC94DCB5BE@suse.de> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] ahci: add port I/O index-data pair List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Daniel Verkamp Cc: Kevin Wolf , qemu-devel@nongnu.org On 08/30/2011 05:07 AM, Daniel Verkamp wrote: > On Sun, Aug 28, 2011 at 11:48 AM, Alexander Graf wrote: >> On 27.08.2011, at 04:12, Daniel Verkamp wrote: >> >>> Implement an I/O space index-data register pair as defined by the AHCI >>> spec, including the corresponding SATA PCI capability and BAR. >>> >>> This allows real-mode code to access the AHCI registers; real-mode >>> code cannot address the memory-mapped register space because it is >>> beyond the first megabyte. >> Very nice patch! I'll check and compare with a real ICH-9 when I get >> back to .de, but I'd assume you also did that already ;). Once I checked >> that the IO region is set up similarly, I'll give you my ack. > Please do double check against real hardware if you get the chance - I > don't have a real ICH-9 handy to test against. This is all written > based on my reading of the spec and testing with an internal DOS > developer tool from work. > > I am mainly curious how the real thing handles writes to the index > register that aren't divisible by 4 or are beyond the end of the > register set (and how big that really is on ICH-9). Judging by the > bits marked "RO" in the spec, I would guess writing 0x13 to the index > and then reading it back should give 0x10, but I haven't tested it on > real hw. Phew. So I finally got at least an ICH-9 system booting. This is what lspci -vvv tells me: 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- Kernel driver in use: ahci So BAR4 is where the IDP info should be. Offset is 4 into that IO space and the space is 32 bytes long. Do you have the ICH-9 implementation spec? I can try to dig something up if you don't have it around. Please send me a small test program I can run on the machine to find out what happens for unaligned I/O accesses. That would be very helpful! Thanks, Alex