From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33689) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qz9m6-0005mX-17 for qemu-devel@nongnu.org; Thu, 01 Sep 2011 12:05:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qz9m4-0004DG-E5 for qemu-devel@nongnu.org; Thu, 01 Sep 2011 12:05:53 -0400 Received: from mail-yw0-f45.google.com ([209.85.213.45]:59068) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qz9m4-0004Cb-8w for qemu-devel@nongnu.org; Thu, 01 Sep 2011 12:05:52 -0400 Received: by ywf9 with SMTP id 9so1666824ywf.4 for ; Thu, 01 Sep 2011 09:05:51 -0700 (PDT) Message-ID: <4E5FAD5C.4090208@codemonkey.ws> Date: Thu, 01 Sep 2011 11:05:48 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <1314853263-2086-1-git-send-email-david@gibson.dropbear.id.au> <1314853263-2086-2-git-send-email-david@gibson.dropbear.id.au> <4E5FAADF.1040704@us.ibm.com> <4E5FACD6.9000603@redhat.com> In-Reply-To: <4E5FACD6.9000603@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 01/10] Add stub functions for PCI device models to do PCI DMA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Anthony Liguori , joerg.roedel@amd.com, agraf@suse.de, qemu-devel@nongnu.org, eduard.munteanu@linux360.ro, rth@twiddle.net, David Gibson On 09/01/2011 11:03 AM, Avi Kivity wrote: > On 09/01/2011 06:55 PM, Anthony Liguori wrote: >> On 09/01/2011 12:00 AM, David Gibson wrote: >>> This patch adds functions to pci.[ch] to perform PCI DMA operations. At >>> present, these are just stubs which perform directly cpu physical memory >>> accesses. >>> >>> Using these stubs, however, distinguishes PCI device DMA transactions >>> from >>> other accesses to physical memory, which will allow PCI IOMMU support to >>> be added in one place, rather than updating every PCI driver at that >>> time. >>> >>> That is, it allows us to update individual PCI drivers to support an >>> IOMMU >>> without having yet determined the details of how the IOMMU emulation >>> will >>> operate. This will let us remove the most bitrot-sensitive part of an >>> IOMMU patch in advance. >>> >>> Signed-off-by: David Gibson >> >> I think this is the wrong approach given the introduction of the >> memory API. >> >> I think we should have a generic memory access function that takes a >> MemoryRegion as it's first argument. >> >> The PCI bus should then expose one memory region for each device >> (that's how it can figure out where the access is coming from). >> >> Richard/Avi, what do you think? >> > > I think the patchset is fine. It routes all access through pci_dma_rw(), > which accepts a PCIDevice. We can later define pci_dma_rw() in terms of > the memory API and get the benefit of the memory hierarchy. The challenge is what you do about something like ne2k where the core chipset can either be a PCI device or an ISA device. You would have to implement a wrapper around pci_dma_rw() in order to turn it into cpu_physical_memory_rw when doing ISA. Regards, Anthony Liguori >