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Date: Fri, 02 Sep 2011 08:11:29 +0200
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Subject: Re: [Qemu-devel] [PATCH] virtio: Make memory barriers be memory
	barriers
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To: "Michael S. Tsirkin" <mst@redhat.com>, aliguori@us.ibm.com, aik@ozlabs.ru, rusty@rustcorp.com.au, qemu-devel@nongnu.org, agraf@suse.de

On 09/02/2011 02:11 AM, David Gibson wrote:
>>> >  >Why not limit the change to ppc then?
>> >
>> >  Because the bug is masked by the x86 memory model, but it is still
>> >  there even there conceptually.  It is not really true that x86 does
>> >  not need memory barriers, though it doesn't in this case:
>> >
>> >  http://bartoszmilewski.wordpress.com/2008/11/05/who-ordered-memory-fences-on-an-x86/
> Not to mention that pcc is not the only non-x86 architecture.  I don't
> know all their storage models off hand, but the point is that there is
> a required order to these writes, so there should be a memory barrier.

Indeed, I interpreted Michael's question more as "why not limit the 
change to non-x86".  I think we should cater to all memory models except 
perhaps the Alpha's.

Paolo