[Qemu-devel] [PATCH 0/5] Only one call output register needed for 64 bit hosts

[Qemu-devel] [PATCH 0/5] Only one call output register needed for 64 bit hosts

[Stefan Weil]

The number of registers needed for the return value of TCG opcode
INDEX_op_call is calculated in function tcg_gen_callN (nb_rets).

It can be 0 or 1, for 32 bit hosts also 2 (return 64 bit value in
two 32 bit registers).

Some TCG implementations reserve 2 registers although only 1 is used.
The following patches fix this.

[PATCH 1/5] tcg/i386: Only one call output register needed for 64 bit hosts
[PATCH 2/5] tcg/ia64: Only one call output register needed for 64 bit hosts
[PATCH 3/5] tcg/s390: Only one call output register needed for 64 bit hosts
[PATCH 4/5] tcg/sparc: Only one call output register needed for 64 bit hosts
[PATCH 5/5] tcg/ppc64: Only one call output register needed for 64 bit hosts

[Qemu-devel] [PATCH 1/5] tcg/i386: Only one call output register needed for 64 bit hosts

[Stefan Weil]

The second register is only needed for 32 bit hosts.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
---
 tcg/i386/tcg-target.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 7529677..281f87d 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -76,9 +76,11 @@ static const int tcg_target_call_iarg_regs[] = {
 #endif
 };
 
-static const int tcg_target_call_oarg_regs[2] = {
+static const int tcg_target_call_oarg_regs[] = {
     TCG_REG_EAX,
+#if TCG_TARGET_REG_BITS == 32
     TCG_REG_EDX
+#endif
 };
 
 static uint8_t *tb_ret_addr;
-- 
1.7.0.4

[Qemu-devel] [PATCH 2/5] tcg/ia64: Only one call output register needed for 64 bit hosts

[Stefan Weil]

The second register is never used for ia64 hosts.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
---
 tcg/ia64/tcg-target.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 9db205d..3803ab6 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -172,9 +172,8 @@ static const int tcg_target_call_iarg_regs[8] = {
     TCG_REG_R63,
 };
 
-static const int tcg_target_call_oarg_regs[2] = {
-    TCG_REG_R8,
-    TCG_REG_R9
+static const int tcg_target_call_oarg_regs[] = {
+    TCG_REG_R8
 };
 
 /* maximum number of register used for input function arguments */
-- 
1.7.0.4

[Qemu-devel] [PATCH 3/5] tcg/s390: Only one call output register needed for 64 bit hosts

[Stefan Weil]

The second register is only needed for 32 bit hosts.

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
---
 tcg/s390/tcg-target.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 2fc5646..b58df71 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -252,7 +252,9 @@ static const int tcg_target_call_iarg_regs[] = {
 
 static const int tcg_target_call_oarg_regs[] = {
     TCG_REG_R2,
-    TCG_REG_R3,
+#if TCG_TARGET_REG_BITS == 32
+    TCG_REG_R3
+#endif
 };
 
 #define S390_CC_EQ      8
-- 
1.7.0.4

[Qemu-devel] [PATCH 4/5] tcg/sparc: Only one call output register needed for 64 bit hosts

[Stefan Weil]

The second register is only needed for 32 bit hosts.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
---
 tcg/sparc/tcg-target.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index ac76e11..fc3fd7f 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -84,9 +84,11 @@ static const int tcg_target_call_iarg_regs[6] = {
     TCG_REG_O5,
 };
 
-static const int tcg_target_call_oarg_regs[2] = {
+static const int tcg_target_call_oarg_regs[] = {
     TCG_REG_O0,
-    TCG_REG_O1,
+#if TCG_TARGET_REG_BITS == 32
+    TCG_REG_O1
+#endif
 };
 
 static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
-- 
1.7.0.4

[Qemu-devel] [PATCH 5/5] tcg/ppc64: Only one call output register needed for 64 bit hosts

[Stefan Weil]

The second register is only needed for 32 bit hosts.

Cc: Vassili Karpov <av1474@comtv.ru>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
---
 tcg/ppc64/tcg-target.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index d831684..bef7aac 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -130,7 +130,7 @@ static const int tcg_target_call_iarg_regs[] = {
     TCG_REG_R10
 };
 
-static const int tcg_target_call_oarg_regs[2] = {
+static const int tcg_target_call_oarg_regs[] = {
     TCG_REG_R3
 };
 
-- 
1.7.0.4

Re: [Qemu-devel] [PATCH 5/5] tcg/ppc64: Only one call output register needed for 64 bit hosts

[malc]

On Mon, 5 Sep 2011, Stefan Weil wrote:

> The second register is only needed for 32 bit hosts.
> 
> Cc: Vassili Karpov <av1474@comtv.ru>
> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
> ---
>  tcg/ppc64/tcg-target.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index d831684..bef7aac 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -130,7 +130,7 @@ static const int tcg_target_call_iarg_regs[] = {
>      TCG_REG_R10
>  };
>  
> -static const int tcg_target_call_oarg_regs[2] = {
> +static const int tcg_target_call_oarg_regs[] = {
>      TCG_REG_R3
>  };
>  

Fine with me. 

-- 
mailto:av1474@comtv.ru

Re: [Qemu-devel] [PATCH 3/5] tcg/s390: Only one call output register needed for 64 bit hosts

[Alexander Graf]

On 05.09.2011, at 11:07, Stefan Weil wrote:

> The second register is only needed for 32 bit hosts.

Looks sane to me. Richard, mind to ack?


Alex

> 
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
> ---
> tcg/s390/tcg-target.c |    4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
> 
> diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
> index 2fc5646..b58df71 100644
> --- a/tcg/s390/tcg-target.c
> +++ b/tcg/s390/tcg-target.c
> @@ -252,7 +252,9 @@ static const int tcg_target_call_iarg_regs[] = {
> 
> static const int tcg_target_call_oarg_regs[] = {
>     TCG_REG_R2,
> -    TCG_REG_R3,
> +#if TCG_TARGET_REG_BITS == 32
> +    TCG_REG_R3
> +#endif
> };
> 
> #define S390_CC_EQ      8
> -- 
> 1.7.0.4
> 

Re: [Qemu-devel] [PATCH 3/5] tcg/s390: Only one call output register needed for 64 bit hosts

[Richard Henderson]

On 09/07/2011 12:32 PM, Alexander Graf wrote:
> 
> On 05.09.2011, at 11:07, Stefan Weil wrote:
> 
>> The second register is only needed for 32 bit hosts.
> 
> Looks sane to me. Richard, mind to ack?
> 
> 
> Alex
> 
>>
>> Cc: Alexander Graf <agraf@suse.de>
>> Signed-off-by: Stefan Weil <weil@mail.berlios.de>

Acked-by: Richard Henderson <rth@twiddle.net>


r~

Re: [Qemu-devel] [PATCH 0/5] Only one call output register needed for 64 bit hosts

[Stefan Weil]

Am 05.09.2011 11:06, schrieb Stefan Weil:
> The number of registers needed for the return value of TCG opcode
> INDEX_op_call is calculated in function tcg_gen_callN (nb_rets).
>
> It can be 0 or 1, for 32 bit hosts also 2 (return 64 bit value in
> two 32 bit registers).
>
> Some TCG implementations reserve 2 registers although only 1 is used.
> The following patches fix this.
>
> [PATCH 1/5] tcg/i386: Only one call output register needed for 64 bit 
> hosts
> [PATCH 2/5] tcg/ia64: Only one call output register needed for 64 bit 
> hosts
> [PATCH 3/5] tcg/s390: Only one call output register needed for 64 bit 
> hosts
> [PATCH 4/5] tcg/sparc: Only one call output register needed for 64 bit 
> hosts
> [PATCH 5/5] tcg/ppc64: Only one call output register needed for 64 bit 
> hosts

Patch 3 was acked by Richard Henderson, so was patch 5 by Malc.

What about the other three patches (i386 / ia64, sparc)? They are all 
similar,
so I think they could also be committed without more reviews.

Thanks,
Stefan Weil

Re: [Qemu-devel] [PATCH 0/5] Only one call output register needed for 64 bit hosts

[Blue Swirl]

Thanks, applied all.

On Sat, Sep 17, 2011 at 2:01 PM, Stefan Weil <weil@mail.berlios.de> wrote:
> Am 05.09.2011 11:06, schrieb Stefan Weil:
>>
>> The number of registers needed for the return value of TCG opcode
>> INDEX_op_call is calculated in function tcg_gen_callN (nb_rets).
>>
>> It can be 0 or 1, for 32 bit hosts also 2 (return 64 bit value in
>> two 32 bit registers).
>>
>> Some TCG implementations reserve 2 registers although only 1 is used.
>> The following patches fix this.
>>
>> [PATCH 1/5] tcg/i386: Only one call output register needed for 64 bit
>> hosts
>> [PATCH 2/5] tcg/ia64: Only one call output register needed for 64 bit
>> hosts
>> [PATCH 3/5] tcg/s390: Only one call output register needed for 64 bit
>> hosts
>> [PATCH 4/5] tcg/sparc: Only one call output register needed for 64 bit
>> hosts
>> [PATCH 5/5] tcg/ppc64: Only one call output register needed for 64 bit
>> hosts
>
> Patch 3 was acked by Richard Henderson, so was patch 5 by Malc.
>
> What about the other three patches (i386 / ia64, sparc)? They are all
> similar,
> so I think they could also be committed without more reviews.
>
> Thanks,
> Stefan Weil
>
>