From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([140.186.70.92]:34971)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1R8bJw-00088a-Uq
	for qemu-devel@nongnu.org; Tue, 27 Sep 2011 13:19:54 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1R8bJv-0004LA-OD
	for qemu-devel@nongnu.org; Tue, 27 Sep 2011 13:19:52 -0400
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <4E8205AE.5060809@twiddle.net>
Date: Tue, 27 Sep 2011 10:19:42 -0700
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1315989802-18753-1-git-send-email-agraf@suse.de>
	<1315989802-18753-25-git-send-email-agraf@suse.de>
	<CAAu8pHv=4XDycKpWL-4XAMteMekf7dsWThqmO1ONS6tHQPHAjw@mail.gmail.com>
	<C220D5FE-87F1-465D-8803-D84F9D88AD15@suse.de>
	<CAAu8pHtDDZLxemWPQzEFiRDw-JH28nyFPQXs+a-JXUg7ND8O3Q@mail.gmail.com>
	<14529F4D-D8AC-4097-8DF8-5F13EDCCC77F@suse.de>
	<4E7769D0.3090909@freescale.com>
	<CAAu8pHuaFSooFf7Ea57TTTE=8AOdmCN0DMHNZBihOpmn-VKH9Q@mail.gmail.com>
	<1CECB54D-1FED-4AC2-B86B-8082CCFE001F@suse.de>
	<CAAu8pHteYfHVC7wfBRfwh1pYk64i9cRi_tUb=2_yY_x88sncCw@mail.gmail.com>
	<D803B0B1-4DC8-4F1D-BA25-5E098FF68D56@suse.de>
	<4E810883.4010405@freescale.com>
	<CAAu8pHsOwjL7eqL+1zD0ZEgW_tf0Btmek+J0wZMQePiw1wVvFA@mail.gmail.com>
	<DD1EC171-E182-453D-B463-A14704F1FB5D@suse.de>
	<CAAu8pHuhnXnULeqZP2X1gr740LiF7yH12dL9RDtY-_d0dd7qyw@mail.gmail.com>
	<4E820186.3090505@twiddle.net>
	<CAAu8pHv8GkEsxDnKq81XLFnEcqgs+CcLShJnDWGyhcDgcExWcQ@mail.gmail.com>
In-Reply-To: <CAAu8pHv8GkEsxDnKq81XLFnEcqgs+CcLShJnDWGyhcDgcExWcQ@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH 24/58] PPC: E500: Add PV spinning code
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: Alexander Graf <agraf@suse.de>, qemu-devel Developers <qemu-devel@nongnu.org>, Yoder Stuart-B08248 <b08248@freescale.com>, qemu-ppc@nongnu.org, Scott Wood <scottwood@freescale.com>, Aurelien Jarno <aurelien@aurel32.net>

On 09/27/2011 10:17 AM, Blue Swirl wrote:
> On Tue, Sep 27, 2011 at 5:01 PM, Richard Henderson <rth@twiddle.net> wrote:
>> On 09/27/2011 09:53 AM, Blue Swirl wrote:
>>>>> So how would you emulate cache lines with line locking on KVM?
>>> The cache would be a MMIO device which registers to handle all memory
>>> space. Configuring the cache controller changes how the device
>>> operates. Put this device between CPU and memory and other devices.
>>> Performance would probably be horrible, so CPU should disable the
>>> device automatically after some time.
>>>
>>
>> Seems like a better alternative would be to add an mmio device when
>> a line is actually locked.  And the device would cover *only* the
>> locked line.  I assume that following the boot process these lines
>> are unlocked, and the normal running state of the system would have
>> none of these mmio devices active.
> 
> The BIOS may also attempt to perform tests with the cache device,
> probe for cache sizes or read back I/D TLB lines via diagnostic modes.
> That wouldn't work in your approach.

Err... why not?


r~