From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R8vRr-0007zs-V7 for qemu-devel@nongnu.org; Wed, 28 Sep 2011 10:49:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R8vRq-0005dW-RW for qemu-devel@nongnu.org; Wed, 28 Sep 2011 10:49:23 -0400 Message-ID: <4E8333DF.1080504@siemens.com> Date: Wed, 28 Sep 2011 16:49:03 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <4E832DE3.40503@siemens.com> <5B15DB32-18DF-4637-AD37-4BE652A031E3@suse.de> <4E83330C.2080901@siemens.com> In-Reply-To: <4E83330C.2080901@siemens.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: "qemu-ppc@nongnu.org" , qemu-devel Developers , kvm , David Gibson On 2011-09-28 16:45, Jan Kiszka wrote: > On 2011-09-28 16:26, Alexander Graf wrote: >> >> On 28.09.2011, at 16:23, Jan Kiszka wrote: >> >>> Alex, >>> >>> we have this diff in qemu-kvm: >>> >>> diff --git a/exec.c b/exec.c >>> index c1e045d..f188549 100644 >>> --- a/exec.c >>> +++ b/exec.c >>> @@ -3950,6 +3955,11 @@ void cpu_physical_memory_rw(target_phys_addr_t >>> addr, uint8_t *buf, >>> cpu_physical_memory_set_dirty_flags( >>> addr1, (0xff& ~CODE_DIRTY_FLAG)); >>> } >>> + /* qemu doesn't execute guest code directly, but kvm does >>> + therefore flush instruction caches */ >>> + if (kvm_enabled()) >>> + flush_icache_range((unsigned long)ptr, >>> + ((unsigned long)ptr)+l); >>> qemu_put_ram_ptr(ptr); >>> } >>> } else { >>> >>> >>> flush_icache_range() is doing something only on PPC hosts. So do we need >>> this upstream? >> >> This makes sure that when device emulation overwrites code that is >> already present in the cache of a CPU, it gets flushed from the >> icache. I'm fairly sure we want that :). But let's ask Ben and David >> as well. > > /me wondered which write scenario precisely needs this. It could only be > something synchronous /wrt to some VCPU. Which operations could trigger > such a write? Does PPC inject software breakpoints in form of trap > operations or so? > > Mmm, according to our ancient recordings, the hunk above was once > introduced for the sake of IA64: 9dc99a2823. I skipped it in my removal > patch as it has some non-IA64 effect, at least potentially. Correction: It was introduced by 6d3295f7c8, but generalized with f067512c06. That former commit talks about DMA operations on IA64 that also updates/drops the icache in reality. Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux