From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:55262) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RC9iQ-0005wV-Sm for qemu-devel@nongnu.org; Fri, 07 Oct 2011 08:39:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RC9iN-0008Pj-3r for qemu-devel@nongnu.org; Fri, 07 Oct 2011 08:39:50 -0400 Message-ID: <4E8EF34F.3010309@suse.de> Date: Fri, 07 Oct 2011 14:40:47 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1317225245-24360-1-git-send-email-chouteau@adacore.com> In-Reply-To: <1317225245-24360-1-git-send-email-chouteau@adacore.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] Set an invalid-bits mask for each SPE instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabien Chouteau Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 09/28/2011 05:54 PM, Fabien Chouteau wrote: > SPE instructions are defined by pairs. Currently, the invalid-bits mask is set > for the first instruction, but the second one can have a different mask. > > example: > GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), > > Signed-off-by: Fabien Chouteau It certainly doesn't make the code more ugly than it was before :). Applied to my local ppc-next branch. I take it that you verified all the invalid masks are sane. There are some lines exceeding 80 characters, but I'm fairly sure they did before too. So I'll let this slip through for the sake of readability. Alex