From: "Andreas Färber" <afaerber@suse.de>
To: Dmitry Koshelev <karaghiozis@gmail.com>
Cc: qemu-trivial@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
qemu-devel@nongnu.org, paul@codesourcery.com
Subject: Re: [Qemu-devel] [PATCH] ARM GIC and CPU state saving/loading fix
Date: Fri, 14 Oct 2011 16:57:24 +0200 [thread overview]
Message-ID: <4E984DD4.50608@suse.de> (raw)
In-Reply-To: <CAKUHwZpxH2vUBb9Y_R0uPCMvPhcpNB=yJJFdmJFWfmtbG85_Nw@mail.gmail.com>
Am 14.10.2011 15:25, schrieb Dmitry Koshelev:
> Fixes two trivial indices errors.
>
> Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com>
> ---
> hw/arm_gic.c | 12 ++++++------
> target-arm/machine.c | 4 ++--
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index 8286a28..ba05131 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -662,9 +662,6 @@ static void gic_save(QEMUFile *f, void *opaque)
> qemu_put_be32(f, s->enabled);
> for (i = 0; i < NUM_CPU(s); i++) {
> qemu_put_be32(f, s->cpu_enabled[i]);
> -#ifndef NVIC
> - qemu_put_be32(f, s->irq_target[i]);
> -#endif
> for (j = 0; j < 32; j++)
> qemu_put_be32(f, s->priority1[j][i]);
> for (j = 0; j < GIC_NIRQ; j++)
> @@ -678,6 +675,9 @@ static void gic_save(QEMUFile *f, void *opaque)
> qemu_put_be32(f, s->priority2[i]);
> }
> for (i = 0; i < GIC_NIRQ; i++) {
> +#ifndef NVIC
> + qemu_put_be32(f, s->irq_target[i]);
> +#endif
> qemu_put_byte(f, s->irq_state[i].enabled);
> qemu_put_byte(f, s->irq_state[i].pending);
> qemu_put_byte(f, s->irq_state[i].active);
> @@ -699,9 +699,6 @@ static int gic_load(QEMUFile *f, void *opaque, int
> version_id)
> s->enabled = qemu_get_be32(f);
> for (i = 0; i < NUM_CPU(s); i++) {
> s->cpu_enabled[i] = qemu_get_be32(f);
> -#ifndef NVIC
> - s->irq_target[i] = qemu_get_be32(f);
> -#endif
> for (j = 0; j < 32; j++)
> s->priority1[j][i] = qemu_get_be32(f);
> for (j = 0; j < GIC_NIRQ; j++)
> @@ -715,6 +712,9 @@ static int gic_load(QEMUFile *f, void *opaque, int
> version_id)
> s->priority2[i] = qemu_get_be32(f);
> }
> for (i = 0; i < GIC_NIRQ; i++) {
> +#ifndef NVIC
> + s->irq_target[i] = qemu_get_be32(f);
> +#endif
> s->irq_state[i].enabled = qemu_get_byte(f);
> s->irq_state[i].pending = qemu_get_byte(f);
> s->irq_state[i].active = qemu_get_byte(f);
This part:
Reviewed-by: Andreas Färber <afaerber@suse.de>
The definition is int irq_target[GIC_NIRQ] and not [NCPU] as others.
The following part however is totally unrelated and should be put in a
separate patch. Both are non-trivial, please cc Peter Maydell instead.
> diff --git a/target-arm/machine.c b/target-arm/machine.c
> index 3925d3a..1b1b3ec 100644
> --- a/target-arm/machine.c
> +++ b/target-arm/machine.c
> @@ -53,7 +53,7 @@ void cpu_save(QEMUFile *f, void *opaque)
> qemu_put_be32(f, env->features);
>
> if (arm_feature(env, ARM_FEATURE_VFP)) {
> - for (i = 0; i < 16; i++) {
> + for (i = 16; i < 32; i++) {
> CPU_DoubleU u;
> u.d = env->vfp.regs[i];
> qemu_put_be32(f, u.l.upper);
> @@ -175,7 +175,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
> env->vfp.vec_stride = qemu_get_be32(f);
>
> if (arm_feature(env, ARM_FEATURE_VFP3)) {
> - for (i = 0; i < 16; i++) {
> + for (i = 16; i < 32; i++) {
> CPU_DoubleU u;
> u.l.upper = qemu_get_be32(f);
> u.l.lower = qemu_get_be32(f);
>
This does not look fully right either way... In addition, it touches the
storage format so any change there may require a version bump.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746, AG Nürnberg
next prev parent reply other threads:[~2011-10-14 14:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-14 13:25 [Qemu-devel] [PATCH] ARM GIC and CPU state saving/loading fix Dmitry Koshelev
2011-10-14 13:50 ` Stefan Hajnoczi
2011-10-14 14:57 ` Andreas Färber [this message]
2011-10-14 15:04 ` Paul Brook
2011-10-14 17:07 ` Dmitry Koshelev
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