From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:50230) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1REjCW-00031Z-IP for qemu-devel@nongnu.org; Fri, 14 Oct 2011 10:57:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1REjCQ-0001vF-6k for qemu-devel@nongnu.org; Fri, 14 Oct 2011 10:57:32 -0400 Message-ID: <4E984DD4.50608@suse.de> Date: Fri, 14 Oct 2011 16:57:24 +0200 From: =?ISO-8859-1?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] ARM GIC and CPU state saving/loading fix List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Dmitry Koshelev Cc: qemu-trivial@nongnu.org, Peter Maydell , qemu-devel@nongnu.org, paul@codesourcery.com Am 14.10.2011 15:25, schrieb Dmitry Koshelev: > Fixes two trivial indices errors. >=20 > Signed-off-by: Dmitry Koshelev > --- > hw/arm_gic.c | 12 ++++++------ > target-arm/machine.c | 4 ++-- > 2 files changed, 8 insertions(+), 8 deletions(-) >=20 > diff --git a/hw/arm_gic.c b/hw/arm_gic.c > index 8286a28..ba05131 100644 > --- a/hw/arm_gic.c > +++ b/hw/arm_gic.c > @@ -662,9 +662,6 @@ static void gic_save(QEMUFile *f, void *opaque) > qemu_put_be32(f, s->enabled); > for (i =3D 0; i < NUM_CPU(s); i++) { > qemu_put_be32(f, s->cpu_enabled[i]); > -#ifndef NVIC > - qemu_put_be32(f, s->irq_target[i]); > -#endif > for (j =3D 0; j < 32; j++) > qemu_put_be32(f, s->priority1[j][i]); > for (j =3D 0; j < GIC_NIRQ; j++) > @@ -678,6 +675,9 @@ static void gic_save(QEMUFile *f, void *opaque) > qemu_put_be32(f, s->priority2[i]); > } > for (i =3D 0; i < GIC_NIRQ; i++) { > +#ifndef NVIC > + qemu_put_be32(f, s->irq_target[i]); > +#endif > qemu_put_byte(f, s->irq_state[i].enabled); > qemu_put_byte(f, s->irq_state[i].pending); > qemu_put_byte(f, s->irq_state[i].active); > @@ -699,9 +699,6 @@ static int gic_load(QEMUFile *f, void *opaque, int > version_id) > s->enabled =3D qemu_get_be32(f); > for (i =3D 0; i < NUM_CPU(s); i++) { > s->cpu_enabled[i] =3D qemu_get_be32(f); > -#ifndef NVIC > - s->irq_target[i] =3D qemu_get_be32(f); > -#endif > for (j =3D 0; j < 32; j++) > s->priority1[j][i] =3D qemu_get_be32(f); > for (j =3D 0; j < GIC_NIRQ; j++) > @@ -715,6 +712,9 @@ static int gic_load(QEMUFile *f, void *opaque, int > version_id) > s->priority2[i] =3D qemu_get_be32(f); > } > for (i =3D 0; i < GIC_NIRQ; i++) { > +#ifndef NVIC > + s->irq_target[i] =3D qemu_get_be32(f); > +#endif > s->irq_state[i].enabled =3D qemu_get_byte(f); > s->irq_state[i].pending =3D qemu_get_byte(f); > s->irq_state[i].active =3D qemu_get_byte(f); This part: Reviewed-by: Andreas F=E4rber The definition is int irq_target[GIC_NIRQ] and not [NCPU] as others. The following part however is totally unrelated and should be put in a separate patch. Both are non-trivial, please cc Peter Maydell instead. > diff --git a/target-arm/machine.c b/target-arm/machine.c > index 3925d3a..1b1b3ec 100644 > --- a/target-arm/machine.c > +++ b/target-arm/machine.c > @@ -53,7 +53,7 @@ void cpu_save(QEMUFile *f, void *opaque) > qemu_put_be32(f, env->features); >=20 > if (arm_feature(env, ARM_FEATURE_VFP)) { > - for (i =3D 0; i < 16; i++) { > + for (i =3D 16; i < 32; i++) { > CPU_DoubleU u; > u.d =3D env->vfp.regs[i]; > qemu_put_be32(f, u.l.upper); > @@ -175,7 +175,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version= _id) > env->vfp.vec_stride =3D qemu_get_be32(f); >=20 > if (arm_feature(env, ARM_FEATURE_VFP3)) { > - for (i =3D 0; i < 16; i++) { > + for (i =3D 16; i < 32; i++) { > CPU_DoubleU u; > u.l.upper =3D qemu_get_be32(f); > u.l.lower =3D qemu_get_be32(f); >=20 This does not look fully right either way... In addition, it touches the storage format so any change there may require a version bump. Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746, AG N=FCrnb= erg