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Date: Sun, 16 Oct 2011 14:22:44 +0200
From: Jan Kiszka <jan.kiszka@web.de>
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Subject: Re: [Qemu-devel] [PATCH v2 00/23] Rework i8259 and PC interrupt
	models
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To: malc <av1474@comtv.ru>
Cc: Blue Swirl <blauwirbel@gmail.com>, Anthony Liguori <aliguori@us.ibm.com>, qemu-devel <qemu-devel@nongnu.org>, =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= <andreas.faerber@web.de>

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On 2011-10-16 14:07, malc wrote:
> On Sun, 16 Oct 2011, Blue Swirl wrote:
>=20
>> Thanks, applied all.
>>
>> On Fri, Oct 7, 2011 at 7:19 AM, Jan Kiszka <jan.kiszka@siemens.com> wr=
ote:
>>> Highlights of this series:
>>>  - generic i8259, now part of hwlib
>>>  - qdev conversion of i8259
>>>  - fix for i8259 poll mode (and removal of PREP hack)
>>>
>>> The refactoring will also be important to instantiate i8259-kvm devic=
es
>>> for in-kernel irqchip acceleration one day.
>>>
>>> Changes in v2:
>>>  - kept PIC irq state update after reset but clarified why this
>>>   required and only valid here
>>>  - additional fix: Clear ELCR on reset
>=20
> It's not cleared on reset on real hardware..
> http://www.mail-archive.com/qemu-devel@nongnu.org/msg04569.html

It is, see Intel chipset specs.

It is not cleared - and that was likely the bug you once saw - when only
the PIC goes through reset, triggered via an ICWS. But that is handled
as a separate case now, no need to worry.

Jan


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