From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:46047) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RHNDC-0004ch-U9 for qemu-devel@nongnu.org; Fri, 21 Oct 2011 18:05:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RHNDB-0000GS-6x for qemu-devel@nongnu.org; Fri, 21 Oct 2011 18:05:10 -0400 Received: from fmmailgate02.web.de ([217.72.192.227]:51759) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RHNDB-0000G7-0w for qemu-devel@nongnu.org; Fri, 21 Oct 2011 18:05:09 -0400 Message-ID: <4EA1EC91.6050705@web.de> Date: Sat, 22 Oct 2011 00:05:05 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <4DDD4E15.1080404@mcgary.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Sender: andreas.faerber@web.de Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] Multi heterogenous CPU archs for SoC sim? List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Blue Swirl , =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= , =?UTF-8?B?TGx1w61z?= , qemu-devel Developers Am 21.10.2011 08:58, schrieb Peter Maydell: > On 20 October 2011 23:51, Andreas F=C3=A4rber = wrote: >> Renesas announced >> the R-Car H1 this week, a SoC with one SH4A core and four ARM Cortex-A= 9 >> cores. >=20 > Does it expose the SH4 to apps/OSes, or is it mostly used for > power management or similar ignorable duties? The predecessors were all SuperH based only, and the ARM cores don't seem to have VFPv3 so the SH4A would feature a 128-bit FPU. As for what automative customers may do with it once available, I have no clue. My focus is on investigating where QEMU has architectural shortcomings or undocumented assumptions blocking embedded development and addressing these. > (For several > of the ARM boards we currently just ignore the fact that the real > h/w has a Cortex-M3 doing power management type stuff.) Mind to share which boards? I'm only aware of the NXP LPC43xx asymmetric SoC (Cortex-M4 + Cortex-M0), which still is in development stage. The datasheet doesn't really enlighten me how such a combo is supposed to work in shared memory: Do all ARM cores share a reset vector (or what you call it on arm) so that one has to branch based on CPUID to do different tasks on different cores? Andreas