From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:38108) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RHlop-0003kO-Tu for qemu-devel@nongnu.org; Sat, 22 Oct 2011 20:21:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RHloo-0005rg-M1 for qemu-devel@nongnu.org; Sat, 22 Oct 2011 20:21:39 -0400 Received: from fmmailgate02.web.de ([217.72.192.227]:48397) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RHloo-0005rZ-AE for qemu-devel@nongnu.org; Sat, 22 Oct 2011 20:21:38 -0400 Message-ID: <4EA35DC3.90203@web.de> Date: Sun, 23 Oct 2011 02:20:19 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1319116568-2663-1-git-send-email-peter.maydell@linaro.org> <1319116568-2663-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1319116568-2663-5-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-15 Sender: andreas.faerber@web.de Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 4/7] target-arm: Add ARM UDIV/SDIV support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Anthony Liguori , qemu-devel@nongnu.org Am 20.10.2011 15:16, schrieb Peter Maydell: > Add support for UDIV and SDIV in ARM mode. This is a new optional > feature for A profile cores (Thumb mode has had UDIV and SDIV for > M profile cores for some time). >=20 > Signed-off-by: Peter Maydell Lightly ... Tested-by: Andreas F=E4rber Andreas > --- > target-arm/cpu.h | 1 + > target-arm/helper.c | 5 ++++- > target-arm/translate.c | 19 +++++++++++++++++++ > 3 files changed, 24 insertions(+), 1 deletions(-) >=20 > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 00e012e..af3904d 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -375,6 +375,7 @@ enum arm_features { > ARM_FEATURE_V5, > ARM_FEATURE_STRONGARM, > ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ > + ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ > }; > =20 > static inline int arm_feature(CPUARMState *env, int feature) > diff --git a/target-arm/helper.c b/target-arm/helper.c > index faf0283..3a51fd7 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -207,7 +207,7 @@ static void cpu_reset_model_id(CPUARMState *env, ui= nt32_t id) > set_feature(env, ARM_FEATURE_VFP_FP16); > set_feature(env, ARM_FEATURE_NEON); > set_feature(env, ARM_FEATURE_THUMB2EE); > - set_feature(env, ARM_FEATURE_THUMB_DIV); > + set_feature(env, ARM_FEATURE_ARM_DIV); > set_feature(env, ARM_FEATURE_V7MP); > break; > case ARM_CPUID_TI915T: > @@ -261,6 +261,9 @@ static void cpu_reset_model_id(CPUARMState *env, ui= nt32_t id) > if (arm_feature(env, ARM_FEATURE_V7)) { > set_feature(env, ARM_FEATURE_VAPA); > } > + if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { > + set_feature(env, ARM_FEATURE_THUMB_DIV); > + } > } > =20 > void cpu_reset(CPUARMState *env) > diff --git a/target-arm/translate.c b/target-arm/translate.c > index deb0bcf..812a9e7 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7639,6 +7639,25 @@ static void disas_arm_insn(CPUState * env, Disas= Context *s) > store_reg(s, rn, tmp); > } > break; > + case 1: > + case 3: > + /* SDIV, UDIV */ > + if (!arm_feature(env, ARM_FEATURE_ARM_DIV)) { > + goto illegal_op; > + } > + if (((insn >> 5) & 7) || (rd !=3D 15)) { > + goto illegal_op; > + } > + tmp =3D load_reg(s, rm); > + tmp2 =3D load_reg(s, rs); > + if (insn & (1 << 21)) { > + gen_helper_udiv(tmp, tmp, tmp2); > + } else { > + gen_helper_sdiv(tmp, tmp, tmp2); > + } > + tcg_temp_free_i32(tmp2); > + store_reg(s, rn, tmp); > + break; > default: > goto illegal_op; > }