From: Jan Kiszka <jan.kiszka@web.de>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: aliguori@us.ibm.com, pingfank@linux.vnet.ibm.com, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 1/1] Introduce a new bus "ICC" to connect APIC
Date: Sun, 23 Oct 2011 18:00:34 +0200 [thread overview]
Message-ID: <4EA43A22.6030002@web.de> (raw)
In-Reply-To: <CAAu8pHsLcgRCgr3t-0NDfoM=buZMbboRtAPKqeLz-_di-4ft=A@mail.gmail.com>
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On 2011-10-23 17:54, Blue Swirl wrote:
> On Sun, Oct 23, 2011 at 15:45, Jan Kiszka <jan.kiszka@web.de> wrote:
>> On 2011-10-23 14:40, Blue Swirl wrote:
>>> I'm not sure that a full bus is needed for now, even if it could match
>>> real HW better, since the memory API already provides the separation
>>> needed. Perhaps this would be needed later to make IRQs per-CPU also,
>>> or to put IOAPIC also to the bus?
>>
>> The ICC interconnects LAPICs and IOAPICs.
>
> But not between CPU core and its LAPIC?
Nope, that link is core-internal and has nothing to do with the ICC. See
e.g. Figure 2-2 of Intel's "MultiProcessor Specification".
Jan
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next prev parent reply other threads:[~2011-10-23 16:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-19 1:55 [Qemu-devel] [PATCH 1/1] Introduce a new bus "ICC" to connect APIC pingfank
2011-10-19 10:53 ` Jan Kiszka
2011-10-19 12:54 ` Anthony Liguori
2011-10-19 13:33 ` Jan Kiszka
2011-10-19 13:42 ` Jan Kiszka
2011-10-20 6:18 ` liu ping fan
2011-10-23 12:40 ` Blue Swirl
2011-10-23 15:45 ` Jan Kiszka
2011-10-23 15:54 ` Blue Swirl
2011-10-23 16:00 ` Jan Kiszka [this message]
2011-10-25 8:55 ` liu ping fan
2011-10-25 20:24 ` Blue Swirl
2011-10-27 8:41 ` liu ping fan
2011-10-27 20:22 ` Blue Swirl
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