From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:58521) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROAAo-0000XA-L0 for qemu-devel@nongnu.org; Wed, 09 Nov 2011 10:34:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ROAAn-0006yQ-1M for qemu-devel@nongnu.org; Wed, 09 Nov 2011 10:34:46 -0500 Received: from cantor2.suse.de ([195.135.220.15]:32947 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROAAm-0006y9-ME for qemu-devel@nongnu.org; Wed, 09 Nov 2011 10:34:45 -0500 Message-ID: <4EBA9D8D.907@suse.de> Date: Wed, 09 Nov 2011 16:34:37 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1320850979-6620-1-git-send-email-benoit.canet@gmail.com> <1320850979-6620-2-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1320850979-6620-2-git-send-email-benoit.canet@gmail.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 1/2] arm-linux-user: fix elfload.c's AT_HWCAP to reflect cpu features. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-15?Q?Beno=EEt_Canet?= , peter.maydell@linaro.org Cc: qemu-devel@nongnu.org Am 09.11.2011 16:02, schrieb Beno=EEt Canet: > The cpu capabilities passed by the elf loader in AT_HWCAP where were > a constant. > Make AT_HWCAP reflect the emulated cpu features in order to give > correct clues to eglibc. >=20 > Fix : [Bug 887516] [NEW] VFP support reported for the PXA270 >=20 > Signed-off-by: Benoit Canet > --- > linux-user/elfload.c | 43 +++++++++++++++++++++++++++++++++++++++---= - > 1 files changed, 39 insertions(+), 4 deletions(-) >=20 > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index a413976..73c939b 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -330,6 +330,10 @@ enum > ARM_HWCAP_ARM_NEON =3D 1 << 11, > ARM_HWCAP_ARM_VFPv3 =3D 1 << 12, > ARM_HWCAP_ARM_VFPv3D16 =3D 1 << 13, > + ARM_HWCAP_ARM_TLS =3D 1 << 14, > + ARM_HWCAP_ARM_VFPv4 =3D 1 << 15, > + ARM_HWCAP_ARM_IDIVA =3D 1 << 16, > + ARM_HWCAP_ARM_IDIVT =3D 1 << 17, > }; > =20 > #define TARGET_HAS_GUEST_VALIDATE_BASE > @@ -375,10 +379,41 @@ bool guest_validate_base(unsigned long guest_base= ) > return 1; /* All good */ > } > =20 > -#define ELF_HWCAP (ARM_HWCAP_ARM_SWP | ARM_HWCAP_ARM_HALF = \ > - | ARM_HWCAP_ARM_THUMB | ARM_HWCAP_ARM_FAST_MULT = \ > - | ARM_HWCAP_ARM_FPA | ARM_HWCAP_ARM_VFP = \ > - | ARM_HWCAP_ARM_NEON | ARM_HWCAP_ARM_VFPv3 ) > + > +#define ELF_HWCAP get_elf_hwcap() > + > +static uint32_t get_elf_hwcap(void) > +{ > + CPUState *e =3D thread_env; > + uint32_t hwcaps =3D 0; > + > + hwcaps |=3D ARM_HWCAP_ARM_SWP; > + hwcaps |=3D ARM_HWCAP_ARM_HALF; > + hwcaps |=3D ARM_HWCAP_ARM_THUMB; > + hwcaps |=3D ARM_HWCAP_ARM_FAST_MULT; > + > + /* probe for the extra features */ > +#define SET_HWCAP(feat, hwcap) \ > + do {if (arm_feature(e, feat)) { hwcaps |=3D hwcap; } } while (0) Small nit: I notice there's a space missing after do {. I wonder if Coding Style applies to macros, too. In that case this should be five lines. > + SET_HWCAP(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); > + SET_HWCAP(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); > + SET_HWCAP(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); > + SET_HWCAP(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); > + SET_HWCAP(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); > + > + /* Strictly should be ARM_FEATURE_V5TE but we don't distinguish > + * as all our v5 cores are v5TE at the moment > + */ > + SET_HWCAP(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); Peter, usually I'd rather have these things fixed for real before they get forgotten, but I take it this one's for 1.0 and a V5TE feature and V5TE =3D> V5 inference rule would better be saved for 1.1? (I had a serie= s adding inference for V7 =3D> V6 etc. removing duplicated code, not sure i= f I submitted that yet...?) Andreas > + SET_HWCAP(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); > + SET_HWCAP(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); > + SET_HWCAP(ARM_FEATURE_ARM_DIV, ARM_HWCAP_ARM_IDIVA); > + SET_HWCAP(ARM_FEATURE_THUMB_DIV, ARM_HWCAP_ARM_IDIVT); > +#undef SET_HWCAP > + > + return hwcaps; > +} > =20 > #endif > =20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg