From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:38682) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RTKqU-0002H2-TR for qemu-devel@nongnu.org; Wed, 23 Nov 2011 16:59:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RTKqT-0004zO-Tk for qemu-devel@nongnu.org; Wed, 23 Nov 2011 16:59:10 -0500 Received: from mail-vx0-f173.google.com ([209.85.220.173]:42013) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RTKqT-0004zB-RP for qemu-devel@nongnu.org; Wed, 23 Nov 2011 16:59:09 -0500 Received: by vcbfl11 with SMTP id fl11so1977120vcb.4 for ; Wed, 23 Nov 2011 13:59:09 -0800 (PST) Sender: Richard Henderson Message-ID: <4ECD6CA9.9070601@twiddle.net> Date: Wed, 23 Nov 2011 13:59:05 -0800 From: Richard Henderson MIME-Version: 1.0 References: <4EC96838.9000907@web.de> In-Reply-To: <4EC96838.9000907@web.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] Status of the SH4 / ARM7 emulators List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= Cc: Peter Maydell , Renato Utsch , qemu-devel@nongnu.org On 11/20/2011 12:51 PM, Andreas Färber wrote: > * Part of the problem is that common CPUState fields are not at the > start of the struct. I have therefore been playing with a > CPU_COMMON_PREFIX at the start of the struct and using a macro for > clearing on reset, which preserves part of the common prefix fields. Most of the RISC hosts have a limited displacement in their load and store instructions. E.g. 14 bits for Sparc, 12 bits for ARM, 10. We want to be able to load and store the target cpu registers very efficiently. If you move all the common fields to the beginning, that will include the (rather large) TLB tables, and overflow those small offsets. This change would almost certainly be a Large Mistake. r~