From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42846) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXcqk-0000EW-Mp for qemu-devel@nongnu.org; Mon, 05 Dec 2011 13:01:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RXcqj-00056K-C9 for qemu-devel@nongnu.org; Mon, 05 Dec 2011 13:01:10 -0500 Received: from mout.web.de ([212.227.15.4]:62472) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXcqi-00055W-VR for qemu-devel@nongnu.org; Mon, 05 Dec 2011 13:01:09 -0500 Message-ID: <4EDD069F.50401@web.de> Date: Mon, 05 Dec 2011 18:59:59 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1322703478-3292-1-git-send-email-bill4carson@gmail.com> <1322703478-3292-2-git-send-email-bill4carson@gmail.com> In-Reply-To: <1322703478-3292-2-git-send-email-bill4carson@gmail.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] Add minimal Vexpress Cortex A15 support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: bill4carson@gmail.com, peter.maydell@linaro.org Cc: qemu-devel@nongnu.org, android-virt@lists.cs.columbia.edu Am 01.12.2011 02:37, schrieb bill4carson@gmail.com: > From: Bill Carson > > This patch adds minimal codes to support A15 which enables ARM KVM could > run Guest OS build with Versatile Express Cortex-A15x4 tile. > > Signed-off-by: Bill Carson > --- > diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c > new file mode 100644 > index 0000000..2518c17 > --- /dev/null > +++ b/hw/a15mpcore.c > @@ -0,0 +1,118 @@ > +/* > + * ARM A15MPCore internal peripheral emulation (common code). ARM Cortex-A15 MPCore, please. No need to repeat the short file name. > diff --git a/target-arm/helper.c b/target-arm/helper.c > index e712554..6a2c89d 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -217,6 +217,36 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) > env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ > env->cp15.c1_sys = 0x00c50078; > break; > + case ARM_CPUID_CORTEXA15: /* most same as A9 */ > + set_feature(env, ARM_FEATURE_V4T); > + set_feature(env, ARM_FEATURE_V5); > + set_feature(env, ARM_FEATURE_V6); > + set_feature(env, ARM_FEATURE_V6K); > + set_feature(env, ARM_FEATURE_V7); > + set_feature(env, ARM_FEATURE_AUXCR); > + set_feature(env, ARM_FEATURE_THUMB2); > + set_feature(env, ARM_FEATURE_VFP); > + set_feature(env, ARM_FEATURE_VFP3); > + set_feature(env, ARM_FEATURE_VFP_FP16); > + set_feature(env, ARM_FEATURE_NEON); > + set_feature(env, ARM_FEATURE_THUMB2EE); > + /* Note that A9 supports the MP extensions even for > + * A9UP and single-core A9MP (which are both different > + * and valid configurations; we don't model A9UP). > + */ > + set_feature(env, ARM_FEATURE_V7MP); Peter, this calls for my feature inference series. Now that 1.0 is out I'll have another go at it later tonight, adding your suggested rules. Feel free to pick up the initial ones if you like. Andreas