* [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv
@ 2011-12-10 9:02 Andreas Färber
2011-12-10 9:02 ` [Qemu-devel] [PATCH 1/4] tcg: Introduce {MAKE,GET}_TCGV_TL macros Andreas Färber
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Andreas Färber @ 2011-12-10 9:02 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Hello,
Working on 16- and 20-bit targets using TARGET_LONG_BITS == 32, I found it too
easy to accidentally use, e.g., tcg_temp_free() in place of tcg_temp_free_i32().
In case of 78k0/rl78 it may not practically matter yet, but it complicates
going from a 32-bit target to 64 bits, as in the case of arm.
This series refactors TCG code to allow using a dedicated struct for TCGv,
to make variable type mismatches show up as compilation errors.
This series only adds the infrastructure but does not enable it by default.
A series adapting target-i386 will be posted independently as an RFC.
Regards,
Andreas
Cc: Peter Maydell <peter.maydell@linaro.org>
Andreas Färber (4):
tcg: Introduce {MAKE,GET}_TCGV_TL macros
tcg: Convert *_tl*() macros to inline functions
tcg: Update TCGV_{UNUSED,EQUAL}() macros
tcg: Allow to detect TCGv misuses
def-helper.h | 13 +-
tcg/tcg-op.h | 1046 +++++++++++++++++++++++++++++++++++++++++++++++++---------
tcg/tcg.h | 1 +
3 files changed, 896 insertions(+), 164 deletions(-)
--
1.7.7
^ permalink raw reply [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 1/4] tcg: Introduce {MAKE,GET}_TCGV_TL macros 2011-12-10 9:02 [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Andreas Färber @ 2011-12-10 9:02 ` Andreas Färber 2011-12-10 9:02 ` [Qemu-devel] [PATCH 2/4] tcg: Convert *_tl*() macros to inline functions Andreas Färber ` (3 subsequent siblings) 4 siblings, 0 replies; 16+ messages in thread From: Andreas Färber @ 2011-12-10 9:02 UTC (permalink / raw) To: qemu-devel; +Cc: Andreas Färber Signed-off-by: Andreas Färber <andreas.faerber@web.de> --- tcg/tcg-op.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 82e04e7..cbccaef 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2127,6 +2127,8 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #if TARGET_LONG_BITS == 32 #define TCGv TCGv_i32 +#define MAKE_TCGV_TL(x) MAKE_TCGV_I32(x) +#define GET_TCGV_TL(t) GET_TCGV_I32(t) #define tcg_temp_new() tcg_temp_new_i32() #define tcg_global_reg_new tcg_global_reg_new_i32 #define tcg_global_mem_new tcg_global_mem_new_i32 @@ -2138,6 +2140,8 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) #else #define TCGv TCGv_i64 +#define MAKE_TCGV_TL(x) MAKE_TCGV_I64(x) +#define GET_TCGV_TL(t) GET_TCGV_I64(t) #define tcg_temp_new() tcg_temp_new_i64() #define tcg_global_reg_new tcg_global_reg_new_i64 #define tcg_global_mem_new tcg_global_mem_new_i64 -- 1.7.7 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 2/4] tcg: Convert *_tl*() macros to inline functions 2011-12-10 9:02 [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Andreas Färber 2011-12-10 9:02 ` [Qemu-devel] [PATCH 1/4] tcg: Introduce {MAKE,GET}_TCGV_TL macros Andreas Färber @ 2011-12-10 9:02 ` Andreas Färber 2011-12-10 21:06 ` [Qemu-devel] [PATCH v2] " Andreas Färber 2011-12-10 9:02 ` [Qemu-devel] [PATCH 3/4] tcg: Update TCGV_{UNUSED,EQUAL}() macros Andreas Färber ` (2 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Andreas Färber @ 2011-12-10 9:02 UTC (permalink / raw) To: qemu-devel; +Cc: Andreas Färber Using {GET,MAKE}_TCGV_*() on parameters requires properly passing arguments into the macro, so use strongly-typed functions while at it. Signed-off-by: Andreas Färber <andreas.faerber@web.de> --- tcg/tcg-op.h | 1021 +++++++++++++++++++++++++++++++++++++++++++++++++--------- 1 files changed, 866 insertions(+), 155 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index cbccaef..e5c2e37 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2129,30 +2129,89 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #define TCGv TCGv_i32 #define MAKE_TCGV_TL(x) MAKE_TCGV_I32(x) #define GET_TCGV_TL(t) GET_TCGV_I32(t) -#define tcg_temp_new() tcg_temp_new_i32() -#define tcg_global_reg_new tcg_global_reg_new_i32 -#define tcg_global_mem_new tcg_global_mem_new_i32 -#define tcg_temp_local_new() tcg_temp_local_new_i32() -#define tcg_temp_free tcg_temp_free_i32 -#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 -#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) #else #define TCGv TCGv_i64 #define MAKE_TCGV_TL(x) MAKE_TCGV_I64(x) #define GET_TCGV_TL(t) GET_TCGV_I64(t) -#define tcg_temp_new() tcg_temp_new_i64() -#define tcg_global_reg_new tcg_global_reg_new_i64 -#define tcg_global_mem_new tcg_global_mem_new_i64 -#define tcg_temp_local_new() tcg_temp_local_new_i64() -#define tcg_temp_free tcg_temp_free_i64 -#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 -#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) #endif +static inline TCGv tcg_temp_new(void) +{ +#if TARGET_LONG_BITS == 32 + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_temp_new_i32())); +#else + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_temp_new_i64())); +#endif +} + +static inline TCGv tcg_global_reg_new(int reg, const char *name) +{ +#if TARGET_LONG_BITS == 32 + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_global_reg_new_i32(reg, name))); +#else + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_global_reg_new_i64(reg, name))); +#endif +} + +static inline TCGv tcg_global_mem_new(int reg, tcg_target_long offset, + const char *name) +{ +#if TARGET_LONG_BITS == 32 + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_global_mem_new_i32(reg, offset, + name))); +#else + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_global_mem_new_i64(reg, offset, + name))); +#endif +} + +static inline TCGv tcg_temp_local_new(void) +{ +#if TARGET_LONG_BITS == 32 + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_temp_local_new_i32())); +#else + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_temp_local_new_i64())); +#endif +} + +static inline void tcg_temp_free(TCGv v) +{ +#if TARGET_LONG_BITS == 32 + tcg_temp_free_i32(MAKE_TCGV_I32(GET_TCGV_TL(v))); +#else + tcg_temp_free_i64(MAKE_TCGV_I64(GET_TCGV_TL(v))); +#endif +} + +static inline void tcg_gen_qemu_ldst_op(TCGOpcode opc, + TCGv arg1, TCGv arg2, TCGArg arg3) +{ +#if TARGET_LONG_BITS == 32 + tcg_gen_op3i_i32(opc, MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2)), arg3); +#else + tcg_gen_op3i_i64(opc, MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2)), arg3); +#endif +} + +static inline void tcg_gen_qemu_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, + TCGv addr, TCGArg mem_index) +{ +#if TARGET_LONG_BITS == 32 + tcg_gen_qemu_ldst_op_i64_i32(opc, val, MAKE_TCGV_I32(GET_TCGV_TL(addr)), + mem_index); +#else + tcg_gen_qemu_ldst_op_i64_i64(opc, val, MAKE_TCGV_I64(GET_TCGV_TL(addr)), + mem_index); +#endif +} + + /* debug info: write the PC of the corresponding QEMU CPU instruction */ static inline void tcg_gen_debug_insn_start(uint64_t pc) { @@ -2366,150 +2425,802 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) #endif /* TCG_TARGET_REG_BITS != 32 */ + +static inline void tcg_gen_movi_tl(TCGv ret, tcg_target_long arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_movi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg); +#else + tcg_gen_movi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg); +#endif +} + +static inline void tcg_gen_mov_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mov_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ld8u_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld8u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld8u_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld8s_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld8s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld8s_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld16u_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld16u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld16u_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld16s_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld16s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld16s_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld32u_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld32u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld32s_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld32s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_st8_tl(TCGv arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_st8_i64(MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, offset); +#else + tcg_gen_st8_i32(MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, offset); +#endif +} + +static inline void tcg_gen_st16_tl(TCGv arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_st16_i64(MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, offset); +#else + tcg_gen_st16_i32(MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, offset); +#endif +} + +static inline void tcg_gen_st32_tl(TCGv arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_st32_i64(MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, offset); +#else + tcg_gen_st_i32(MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, offset); +#endif +} + +static inline void tcg_gen_st_tl(TCGv arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_st_i64(MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, offset); +#else + tcg_gen_st_i32(MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, offset); +#endif +} + +static inline void tcg_gen_add_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_add_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_add_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_addi_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_addi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_addi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_sub_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_sub_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_sub_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_neg_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_neg_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_neg_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_subfi_tl(TCGv ret, tcg_target_long arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_subfi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg1, + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_subfi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg1, + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_subi_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_subi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_subi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_and_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_and_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_and_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_andi_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_andi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_andi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_or_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_or_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_or_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_ori_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ori_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_ori_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_xor_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_xor_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_xor_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_xori_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_xori_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_xori_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_not_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_not_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_not_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_shl_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_shl_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_shl_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_shli_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_shli_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_shli_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_shr_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_shr_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_shr_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_shri_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_shri_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_sar_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_sar_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_sar_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_sari_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_sari_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_sari_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_brcond_tl(TCGCond cond, TCGv arg1, TCGv arg2, + int label_index) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_brcond_i64(cond, MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2)), label_index); +#else + tcg_gen_brcond_i32(cond, MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2)), label_index); +#endif +} + +static inline void tcg_gen_brcondi_tl(TCGCond cond, TCGv arg1, + tcg_target_long arg2, int label_index) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_brcondi_i64(cond, MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, + label_index); +#else + tcg_gen_brcondi_i32(cond, MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, + label_index); +#endif +} + +static inline void tcg_gen_setcond_tl(TCGCond cond, TCGv ret, + TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_setcond_i64(cond, MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_setcond_i32(cond, MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_setcondi_tl(TCGCond cond, TCGv ret, + TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_setcondi_i64(cond, MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_setcondi_i32(cond, MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_mul_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mul_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_mul_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_muli_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_muli_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_muli_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_div_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_div_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_div_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_rem_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ #if TARGET_LONG_BITS == 64 -#define tcg_gen_movi_tl tcg_gen_movi_i64 -#define tcg_gen_mov_tl tcg_gen_mov_i64 -#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 -#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 -#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 -#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 -#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 -#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 -#define tcg_gen_ld_tl tcg_gen_ld_i64 -#define tcg_gen_st8_tl tcg_gen_st8_i64 -#define tcg_gen_st16_tl tcg_gen_st16_i64 -#define tcg_gen_st32_tl tcg_gen_st32_i64 -#define tcg_gen_st_tl tcg_gen_st_i64 -#define tcg_gen_add_tl tcg_gen_add_i64 -#define tcg_gen_addi_tl tcg_gen_addi_i64 -#define tcg_gen_sub_tl tcg_gen_sub_i64 -#define tcg_gen_neg_tl tcg_gen_neg_i64 -#define tcg_gen_subfi_tl tcg_gen_subfi_i64 -#define tcg_gen_subi_tl tcg_gen_subi_i64 -#define tcg_gen_and_tl tcg_gen_and_i64 -#define tcg_gen_andi_tl tcg_gen_andi_i64 -#define tcg_gen_or_tl tcg_gen_or_i64 -#define tcg_gen_ori_tl tcg_gen_ori_i64 -#define tcg_gen_xor_tl tcg_gen_xor_i64 -#define tcg_gen_xori_tl tcg_gen_xori_i64 -#define tcg_gen_not_tl tcg_gen_not_i64 -#define tcg_gen_shl_tl tcg_gen_shl_i64 -#define tcg_gen_shli_tl tcg_gen_shli_i64 -#define tcg_gen_shr_tl tcg_gen_shr_i64 -#define tcg_gen_shri_tl tcg_gen_shri_i64 -#define tcg_gen_sar_tl tcg_gen_sar_i64 -#define tcg_gen_sari_tl tcg_gen_sari_i64 -#define tcg_gen_brcond_tl tcg_gen_brcond_i64 -#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 -#define tcg_gen_setcond_tl tcg_gen_setcond_i64 -#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 -#define tcg_gen_mul_tl tcg_gen_mul_i64 -#define tcg_gen_muli_tl tcg_gen_muli_i64 -#define tcg_gen_div_tl tcg_gen_div_i64 -#define tcg_gen_rem_tl tcg_gen_rem_i64 -#define tcg_gen_divu_tl tcg_gen_divu_i64 -#define tcg_gen_remu_tl tcg_gen_remu_i64 -#define tcg_gen_discard_tl tcg_gen_discard_i64 -#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 -#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 -#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 -#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 -#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 -#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 -#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 -#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 -#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 -#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 -#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 -#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 -#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 -#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 -#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 -#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 -#define tcg_gen_andc_tl tcg_gen_andc_i64 -#define tcg_gen_eqv_tl tcg_gen_eqv_i64 -#define tcg_gen_nand_tl tcg_gen_nand_i64 -#define tcg_gen_nor_tl tcg_gen_nor_i64 -#define tcg_gen_orc_tl tcg_gen_orc_i64 -#define tcg_gen_rotl_tl tcg_gen_rotl_i64 -#define tcg_gen_rotli_tl tcg_gen_rotli_i64 -#define tcg_gen_rotr_tl tcg_gen_rotr_i64 -#define tcg_gen_rotri_tl tcg_gen_rotri_i64 -#define tcg_gen_deposit_tl tcg_gen_deposit_i64 -#define tcg_const_tl tcg_const_i64 -#define tcg_const_local_tl tcg_const_local_i64 + tcg_gen_rem_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); #else -#define tcg_gen_movi_tl tcg_gen_movi_i32 -#define tcg_gen_mov_tl tcg_gen_mov_i32 -#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 -#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 -#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 -#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 -#define tcg_gen_ld32u_tl tcg_gen_ld_i32 -#define tcg_gen_ld32s_tl tcg_gen_ld_i32 -#define tcg_gen_ld_tl tcg_gen_ld_i32 -#define tcg_gen_st8_tl tcg_gen_st8_i32 -#define tcg_gen_st16_tl tcg_gen_st16_i32 -#define tcg_gen_st32_tl tcg_gen_st_i32 -#define tcg_gen_st_tl tcg_gen_st_i32 -#define tcg_gen_add_tl tcg_gen_add_i32 -#define tcg_gen_addi_tl tcg_gen_addi_i32 -#define tcg_gen_sub_tl tcg_gen_sub_i32 -#define tcg_gen_neg_tl tcg_gen_neg_i32 -#define tcg_gen_subfi_tl tcg_gen_subfi_i32 -#define tcg_gen_subi_tl tcg_gen_subi_i32 -#define tcg_gen_and_tl tcg_gen_and_i32 -#define tcg_gen_andi_tl tcg_gen_andi_i32 -#define tcg_gen_or_tl tcg_gen_or_i32 -#define tcg_gen_ori_tl tcg_gen_ori_i32 -#define tcg_gen_xor_tl tcg_gen_xor_i32 -#define tcg_gen_xori_tl tcg_gen_xori_i32 -#define tcg_gen_not_tl tcg_gen_not_i32 -#define tcg_gen_shl_tl tcg_gen_shl_i32 -#define tcg_gen_shli_tl tcg_gen_shli_i32 -#define tcg_gen_shr_tl tcg_gen_shr_i32 -#define tcg_gen_shri_tl tcg_gen_shri_i32 -#define tcg_gen_sar_tl tcg_gen_sar_i32 -#define tcg_gen_sari_tl tcg_gen_sari_i32 -#define tcg_gen_brcond_tl tcg_gen_brcond_i32 -#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 -#define tcg_gen_setcond_tl tcg_gen_setcond_i32 -#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 -#define tcg_gen_mul_tl tcg_gen_mul_i32 -#define tcg_gen_muli_tl tcg_gen_muli_i32 -#define tcg_gen_div_tl tcg_gen_div_i32 -#define tcg_gen_rem_tl tcg_gen_rem_i32 -#define tcg_gen_divu_tl tcg_gen_divu_i32 -#define tcg_gen_remu_tl tcg_gen_remu_i32 -#define tcg_gen_discard_tl tcg_gen_discard_i32 -#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 -#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 -#define tcg_gen_extu_i32_tl tcg_gen_mov_i32 -#define tcg_gen_ext_i32_tl tcg_gen_mov_i32 -#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 -#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 -#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 -#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 -#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 -#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 -#define tcg_gen_ext32u_tl tcg_gen_mov_i32 -#define tcg_gen_ext32s_tl tcg_gen_mov_i32 -#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 -#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 -#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 -#define tcg_gen_andc_tl tcg_gen_andc_i32 -#define tcg_gen_eqv_tl tcg_gen_eqv_i32 -#define tcg_gen_nand_tl tcg_gen_nand_i32 -#define tcg_gen_nor_tl tcg_gen_nor_i32 -#define tcg_gen_orc_tl tcg_gen_orc_i32 -#define tcg_gen_rotl_tl tcg_gen_rotl_i32 -#define tcg_gen_rotli_tl tcg_gen_rotli_i32 -#define tcg_gen_rotr_tl tcg_gen_rotr_i32 -#define tcg_gen_rotri_tl tcg_gen_rotri_i32 -#define tcg_gen_deposit_tl tcg_gen_deposit_i32 -#define tcg_const_tl tcg_const_i32 -#define tcg_const_local_tl tcg_const_local_i32 + tcg_gen_rem_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); #endif +} + +static inline void tcg_gen_divu_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_divu_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_divu_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_remu_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_remu_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_remu_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_discard_tl(TCGv v) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_discard_i64(MAKE_TCGV_I64(GET_TCGV_TL(v))); +#else + tcg_gen_discard_i32(MAKE_TCGV_I32(GET_TCGV_TL(v))); +#endif +} + +static inline void tcg_gen_trunc_tl_i32(TCGv_i32 ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_trunc_i64_i32(ret, MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_trunc_i64_tl(TCGv ret, TCGv_i64 arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mov_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg); +#else + tcg_gen_trunc_i64_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg); +#endif +} + +static inline void tcg_gen_extu_i32_tl(TCGv ret, TCGv_i32 arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_extu_i32_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg); +#endif +} + +static inline void tcg_gen_ext_i32_tl(TCGv ret, TCGv_i32 arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext_i32_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg); +#endif +} + +static inline void tcg_gen_extu_tl_i64(TCGv_i64 ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mov_i64(ret, MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_extu_i32_i64(ret, MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext_tl_i64(TCGv_i64 ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mov_i64(ret, MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext_i32_i64(ret, MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext8u_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext8u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext8u_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext8s_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext8s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext8s_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext16u_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext16u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext16u_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext16s_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext16s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext16s_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext32u_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext32u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext32s_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext32s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_bswap16_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_bswap16_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_bswap16_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_bswap32_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_bswap32_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_bswap32_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +#if TARGET_LONG_BITS == 64 +static inline void tcg_gen_bswap64_tl(TCGv ret, TCGv arg) +{ + tcg_gen_bswap64_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +} +#endif + +static inline void tcg_gen_concat_tl_i64(TCGv_i64 ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_concat32_i64(ret, MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_concat_i32_i64(ret, MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_andc_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_andc_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_andc_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_eqv_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_eqv_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_eqv_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_nand_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_nand_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_nand_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_nor_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_nor_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_nor_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_orc_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_orc_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_orc_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_rotl_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_rotl_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_rotl_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_rotli_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_rotli_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_rotli_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_rotr_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_rotr_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_rotr_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_rotri_tl(TCGv ret, TCGv arg1, tcg_target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_rotri_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_rotri_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_deposit_tl(TCGv ret, TCGv arg1, TCGv arg2, + unsigned int ofs, unsigned int len) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_deposit_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2)), ofs, len); +#else + tcg_gen_deposit_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2)), ofs, len); +#endif +} + +static inline TCGv tcg_const_tl(tcg_target_long val) +{ +#if TARGET_LONG_BITS == 64 + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_const_i64(val))); +#else + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_const_i32(val))); +#endif +} + +static inline TCGv tcg_const_local_tl(tcg_target_long val) +{ +#if TARGET_LONG_BITS == 64 + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_const_local_i64(val))); +#else + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_const_local_i32(val))); +#endif +} #if TCG_TARGET_REG_BITS == 32 #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \ -- 1.7.7 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v2] tcg: Convert *_tl*() macros to inline functions 2011-12-10 9:02 ` [Qemu-devel] [PATCH 2/4] tcg: Convert *_tl*() macros to inline functions Andreas Färber @ 2011-12-10 21:06 ` Andreas Färber 0 siblings, 0 replies; 16+ messages in thread From: Andreas Färber @ 2011-12-10 21:06 UTC (permalink / raw) To: qemu-devel; +Cc: Andreas Färber Using {GET,MAKE}_TCGV_*() on parameters requires properly passing arguments into the macro, so use strongly-typed functions while at it. Signed-off-by: Andreas Färber <andreas.faerber@web.de> --- v1 -> v2: * Use target_long for immediate arguments, not tcg_target_long tcg/tcg-op.h | 1021 +++++++++++++++++++++++++++++++++++++++++++++++++--------- 1 files changed, 866 insertions(+), 155 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index cbccaef..8fc6a3d 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2129,30 +2129,89 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #define TCGv TCGv_i32 #define MAKE_TCGV_TL(x) MAKE_TCGV_I32(x) #define GET_TCGV_TL(t) GET_TCGV_I32(t) -#define tcg_temp_new() tcg_temp_new_i32() -#define tcg_global_reg_new tcg_global_reg_new_i32 -#define tcg_global_mem_new tcg_global_mem_new_i32 -#define tcg_temp_local_new() tcg_temp_local_new_i32() -#define tcg_temp_free tcg_temp_free_i32 -#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 -#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) #else #define TCGv TCGv_i64 #define MAKE_TCGV_TL(x) MAKE_TCGV_I64(x) #define GET_TCGV_TL(t) GET_TCGV_I64(t) -#define tcg_temp_new() tcg_temp_new_i64() -#define tcg_global_reg_new tcg_global_reg_new_i64 -#define tcg_global_mem_new tcg_global_mem_new_i64 -#define tcg_temp_local_new() tcg_temp_local_new_i64() -#define tcg_temp_free tcg_temp_free_i64 -#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 -#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) #endif +static inline TCGv tcg_temp_new(void) +{ +#if TARGET_LONG_BITS == 32 + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_temp_new_i32())); +#else + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_temp_new_i64())); +#endif +} + +static inline TCGv tcg_global_reg_new(int reg, const char *name) +{ +#if TARGET_LONG_BITS == 32 + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_global_reg_new_i32(reg, name))); +#else + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_global_reg_new_i64(reg, name))); +#endif +} + +static inline TCGv tcg_global_mem_new(int reg, tcg_target_long offset, + const char *name) +{ +#if TARGET_LONG_BITS == 32 + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_global_mem_new_i32(reg, offset, + name))); +#else + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_global_mem_new_i64(reg, offset, + name))); +#endif +} + +static inline TCGv tcg_temp_local_new(void) +{ +#if TARGET_LONG_BITS == 32 + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_temp_local_new_i32())); +#else + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_temp_local_new_i64())); +#endif +} + +static inline void tcg_temp_free(TCGv v) +{ +#if TARGET_LONG_BITS == 32 + tcg_temp_free_i32(MAKE_TCGV_I32(GET_TCGV_TL(v))); +#else + tcg_temp_free_i64(MAKE_TCGV_I64(GET_TCGV_TL(v))); +#endif +} + +static inline void tcg_gen_qemu_ldst_op(TCGOpcode opc, + TCGv arg1, TCGv arg2, TCGArg arg3) +{ +#if TARGET_LONG_BITS == 32 + tcg_gen_op3i_i32(opc, MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2)), arg3); +#else + tcg_gen_op3i_i64(opc, MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2)), arg3); +#endif +} + +static inline void tcg_gen_qemu_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, + TCGv addr, TCGArg mem_index) +{ +#if TARGET_LONG_BITS == 32 + tcg_gen_qemu_ldst_op_i64_i32(opc, val, MAKE_TCGV_I32(GET_TCGV_TL(addr)), + mem_index); +#else + tcg_gen_qemu_ldst_op_i64_i64(opc, val, MAKE_TCGV_I64(GET_TCGV_TL(addr)), + mem_index); +#endif +} + + /* debug info: write the PC of the corresponding QEMU CPU instruction */ static inline void tcg_gen_debug_insn_start(uint64_t pc) { @@ -2366,150 +2425,802 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) #endif /* TCG_TARGET_REG_BITS != 32 */ + +static inline void tcg_gen_movi_tl(TCGv ret, target_long arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_movi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg); +#else + tcg_gen_movi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg); +#endif +} + +static inline void tcg_gen_mov_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mov_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ld8u_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld8u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld8u_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld8s_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld8s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld8s_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld16u_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld16u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld16u_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld16s_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld16s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld16s_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld32u_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld32u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld32s_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld32s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_ld_tl(TCGv ret, TCGv_ptr arg, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ld_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg, offset); +#else + tcg_gen_ld_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg, offset); +#endif +} + +static inline void tcg_gen_st8_tl(TCGv arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_st8_i64(MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, offset); +#else + tcg_gen_st8_i32(MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, offset); +#endif +} + +static inline void tcg_gen_st16_tl(TCGv arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_st16_i64(MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, offset); +#else + tcg_gen_st16_i32(MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, offset); +#endif +} + +static inline void tcg_gen_st32_tl(TCGv arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_st32_i64(MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, offset); +#else + tcg_gen_st_i32(MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, offset); +#endif +} + +static inline void tcg_gen_st_tl(TCGv arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_st_i64(MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, offset); +#else + tcg_gen_st_i32(MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, offset); +#endif +} + +static inline void tcg_gen_add_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_add_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_add_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_addi_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_addi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_addi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_sub_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_sub_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_sub_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_neg_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_neg_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_neg_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_subfi_tl(TCGv ret, target_long arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_subfi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg1, + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_subfi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg1, + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_subi_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_subi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_subi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_and_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_and_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_and_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_andi_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_andi_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_andi_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_or_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_or_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_or_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_ori_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ori_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_ori_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_xor_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_xor_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_xor_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_xori_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_xori_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_xori_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_not_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_not_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_not_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_shl_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_shl_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_shl_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_shli_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_shli_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_shli_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_shr_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_shr_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_shr_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_shri_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_shri_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_sar_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_sar_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_sar_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_sari_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_sari_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_sari_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_brcond_tl(TCGCond cond, TCGv arg1, TCGv arg2, + int label_index) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_brcond_i64(cond, MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2)), label_index); +#else + tcg_gen_brcond_i32(cond, MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2)), label_index); +#endif +} + +static inline void tcg_gen_brcondi_tl(TCGCond cond, TCGv arg1, + target_long arg2, int label_index) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_brcondi_i64(cond, MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2, + label_index); +#else + tcg_gen_brcondi_i32(cond, MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2, + label_index); +#endif +} + +static inline void tcg_gen_setcond_tl(TCGCond cond, TCGv ret, + TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_setcond_i64(cond, MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_setcond_i32(cond, MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_setcondi_tl(TCGCond cond, TCGv ret, + TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_setcondi_i64(cond, MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_setcondi_i32(cond, MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_mul_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mul_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_mul_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_muli_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_muli_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_muli_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_div_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_div_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_div_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_rem_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ #if TARGET_LONG_BITS == 64 -#define tcg_gen_movi_tl tcg_gen_movi_i64 -#define tcg_gen_mov_tl tcg_gen_mov_i64 -#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 -#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 -#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 -#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 -#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 -#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 -#define tcg_gen_ld_tl tcg_gen_ld_i64 -#define tcg_gen_st8_tl tcg_gen_st8_i64 -#define tcg_gen_st16_tl tcg_gen_st16_i64 -#define tcg_gen_st32_tl tcg_gen_st32_i64 -#define tcg_gen_st_tl tcg_gen_st_i64 -#define tcg_gen_add_tl tcg_gen_add_i64 -#define tcg_gen_addi_tl tcg_gen_addi_i64 -#define tcg_gen_sub_tl tcg_gen_sub_i64 -#define tcg_gen_neg_tl tcg_gen_neg_i64 -#define tcg_gen_subfi_tl tcg_gen_subfi_i64 -#define tcg_gen_subi_tl tcg_gen_subi_i64 -#define tcg_gen_and_tl tcg_gen_and_i64 -#define tcg_gen_andi_tl tcg_gen_andi_i64 -#define tcg_gen_or_tl tcg_gen_or_i64 -#define tcg_gen_ori_tl tcg_gen_ori_i64 -#define tcg_gen_xor_tl tcg_gen_xor_i64 -#define tcg_gen_xori_tl tcg_gen_xori_i64 -#define tcg_gen_not_tl tcg_gen_not_i64 -#define tcg_gen_shl_tl tcg_gen_shl_i64 -#define tcg_gen_shli_tl tcg_gen_shli_i64 -#define tcg_gen_shr_tl tcg_gen_shr_i64 -#define tcg_gen_shri_tl tcg_gen_shri_i64 -#define tcg_gen_sar_tl tcg_gen_sar_i64 -#define tcg_gen_sari_tl tcg_gen_sari_i64 -#define tcg_gen_brcond_tl tcg_gen_brcond_i64 -#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 -#define tcg_gen_setcond_tl tcg_gen_setcond_i64 -#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 -#define tcg_gen_mul_tl tcg_gen_mul_i64 -#define tcg_gen_muli_tl tcg_gen_muli_i64 -#define tcg_gen_div_tl tcg_gen_div_i64 -#define tcg_gen_rem_tl tcg_gen_rem_i64 -#define tcg_gen_divu_tl tcg_gen_divu_i64 -#define tcg_gen_remu_tl tcg_gen_remu_i64 -#define tcg_gen_discard_tl tcg_gen_discard_i64 -#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 -#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 -#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 -#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 -#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 -#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 -#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 -#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 -#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 -#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 -#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 -#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 -#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 -#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 -#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 -#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 -#define tcg_gen_andc_tl tcg_gen_andc_i64 -#define tcg_gen_eqv_tl tcg_gen_eqv_i64 -#define tcg_gen_nand_tl tcg_gen_nand_i64 -#define tcg_gen_nor_tl tcg_gen_nor_i64 -#define tcg_gen_orc_tl tcg_gen_orc_i64 -#define tcg_gen_rotl_tl tcg_gen_rotl_i64 -#define tcg_gen_rotli_tl tcg_gen_rotli_i64 -#define tcg_gen_rotr_tl tcg_gen_rotr_i64 -#define tcg_gen_rotri_tl tcg_gen_rotri_i64 -#define tcg_gen_deposit_tl tcg_gen_deposit_i64 -#define tcg_const_tl tcg_const_i64 -#define tcg_const_local_tl tcg_const_local_i64 + tcg_gen_rem_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); #else -#define tcg_gen_movi_tl tcg_gen_movi_i32 -#define tcg_gen_mov_tl tcg_gen_mov_i32 -#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 -#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 -#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 -#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 -#define tcg_gen_ld32u_tl tcg_gen_ld_i32 -#define tcg_gen_ld32s_tl tcg_gen_ld_i32 -#define tcg_gen_ld_tl tcg_gen_ld_i32 -#define tcg_gen_st8_tl tcg_gen_st8_i32 -#define tcg_gen_st16_tl tcg_gen_st16_i32 -#define tcg_gen_st32_tl tcg_gen_st_i32 -#define tcg_gen_st_tl tcg_gen_st_i32 -#define tcg_gen_add_tl tcg_gen_add_i32 -#define tcg_gen_addi_tl tcg_gen_addi_i32 -#define tcg_gen_sub_tl tcg_gen_sub_i32 -#define tcg_gen_neg_tl tcg_gen_neg_i32 -#define tcg_gen_subfi_tl tcg_gen_subfi_i32 -#define tcg_gen_subi_tl tcg_gen_subi_i32 -#define tcg_gen_and_tl tcg_gen_and_i32 -#define tcg_gen_andi_tl tcg_gen_andi_i32 -#define tcg_gen_or_tl tcg_gen_or_i32 -#define tcg_gen_ori_tl tcg_gen_ori_i32 -#define tcg_gen_xor_tl tcg_gen_xor_i32 -#define tcg_gen_xori_tl tcg_gen_xori_i32 -#define tcg_gen_not_tl tcg_gen_not_i32 -#define tcg_gen_shl_tl tcg_gen_shl_i32 -#define tcg_gen_shli_tl tcg_gen_shli_i32 -#define tcg_gen_shr_tl tcg_gen_shr_i32 -#define tcg_gen_shri_tl tcg_gen_shri_i32 -#define tcg_gen_sar_tl tcg_gen_sar_i32 -#define tcg_gen_sari_tl tcg_gen_sari_i32 -#define tcg_gen_brcond_tl tcg_gen_brcond_i32 -#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 -#define tcg_gen_setcond_tl tcg_gen_setcond_i32 -#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 -#define tcg_gen_mul_tl tcg_gen_mul_i32 -#define tcg_gen_muli_tl tcg_gen_muli_i32 -#define tcg_gen_div_tl tcg_gen_div_i32 -#define tcg_gen_rem_tl tcg_gen_rem_i32 -#define tcg_gen_divu_tl tcg_gen_divu_i32 -#define tcg_gen_remu_tl tcg_gen_remu_i32 -#define tcg_gen_discard_tl tcg_gen_discard_i32 -#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 -#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 -#define tcg_gen_extu_i32_tl tcg_gen_mov_i32 -#define tcg_gen_ext_i32_tl tcg_gen_mov_i32 -#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 -#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 -#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 -#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 -#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 -#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 -#define tcg_gen_ext32u_tl tcg_gen_mov_i32 -#define tcg_gen_ext32s_tl tcg_gen_mov_i32 -#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 -#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 -#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 -#define tcg_gen_andc_tl tcg_gen_andc_i32 -#define tcg_gen_eqv_tl tcg_gen_eqv_i32 -#define tcg_gen_nand_tl tcg_gen_nand_i32 -#define tcg_gen_nor_tl tcg_gen_nor_i32 -#define tcg_gen_orc_tl tcg_gen_orc_i32 -#define tcg_gen_rotl_tl tcg_gen_rotl_i32 -#define tcg_gen_rotli_tl tcg_gen_rotli_i32 -#define tcg_gen_rotr_tl tcg_gen_rotr_i32 -#define tcg_gen_rotri_tl tcg_gen_rotri_i32 -#define tcg_gen_deposit_tl tcg_gen_deposit_i32 -#define tcg_const_tl tcg_const_i32 -#define tcg_const_local_tl tcg_const_local_i32 + tcg_gen_rem_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); #endif +} + +static inline void tcg_gen_divu_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_divu_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_divu_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_remu_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_remu_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_remu_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_discard_tl(TCGv v) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_discard_i64(MAKE_TCGV_I64(GET_TCGV_TL(v))); +#else + tcg_gen_discard_i32(MAKE_TCGV_I32(GET_TCGV_TL(v))); +#endif +} + +static inline void tcg_gen_trunc_tl_i32(TCGv_i32 ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_trunc_i64_i32(ret, MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_trunc_i64_tl(TCGv ret, TCGv_i64 arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mov_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg); +#else + tcg_gen_trunc_i64_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg); +#endif +} + +static inline void tcg_gen_extu_i32_tl(TCGv ret, TCGv_i32 arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_extu_i32_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg); +#endif +} + +static inline void tcg_gen_ext_i32_tl(TCGv ret, TCGv_i32 arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext_i32_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), arg); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), arg); +#endif +} + +static inline void tcg_gen_extu_tl_i64(TCGv_i64 ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mov_i64(ret, MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_extu_i32_i64(ret, MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext_tl_i64(TCGv_i64 ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_mov_i64(ret, MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext_i32_i64(ret, MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext8u_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext8u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext8u_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext8s_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext8s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext8s_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext16u_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext16u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext16u_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext16s_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext16s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_ext16s_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext32u_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext32u_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_ext32s_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_ext32s_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_mov_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_bswap16_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_bswap16_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_bswap16_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +static inline void tcg_gen_bswap32_tl(TCGv ret, TCGv arg) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_bswap32_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +#else + tcg_gen_bswap32_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg))); +#endif +} + +#if TARGET_LONG_BITS == 64 +static inline void tcg_gen_bswap64_tl(TCGv ret, TCGv arg) +{ + tcg_gen_bswap64_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg))); +} +#endif + +static inline void tcg_gen_concat_tl_i64(TCGv_i64 ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_concat32_i64(ret, MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_concat_i32_i64(ret, MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_andc_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_andc_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_andc_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_eqv_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_eqv_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_eqv_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_nand_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_nand_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_nand_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_nor_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_nor_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_nor_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_orc_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_orc_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_orc_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_rotl_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_rotl_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_rotl_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_rotli_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_rotli_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_rotli_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_rotr_tl(TCGv ret, TCGv arg1, TCGv arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_rotr_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2))); +#else + tcg_gen_rotr_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2))); +#endif +} + +static inline void tcg_gen_rotri_tl(TCGv ret, TCGv arg1, target_long arg2) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_rotri_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), arg2); +#else + tcg_gen_rotri_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), arg2); +#endif +} + +static inline void tcg_gen_deposit_tl(TCGv ret, TCGv arg1, TCGv arg2, + unsigned int ofs, unsigned int len) +{ +#if TARGET_LONG_BITS == 64 + tcg_gen_deposit_i64(MAKE_TCGV_I64(GET_TCGV_TL(ret)), + MAKE_TCGV_I64(GET_TCGV_TL(arg1)), + MAKE_TCGV_I64(GET_TCGV_TL(arg2)), ofs, len); +#else + tcg_gen_deposit_i32(MAKE_TCGV_I32(GET_TCGV_TL(ret)), + MAKE_TCGV_I32(GET_TCGV_TL(arg1)), + MAKE_TCGV_I32(GET_TCGV_TL(arg2)), ofs, len); +#endif +} + +static inline TCGv tcg_const_tl(target_long val) +{ +#if TARGET_LONG_BITS == 64 + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_const_i64(val))); +#else + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_const_i32(val))); +#endif +} + +static inline TCGv tcg_const_local_tl(target_long val) +{ +#if TARGET_LONG_BITS == 64 + return MAKE_TCGV_TL(GET_TCGV_I64(tcg_const_local_i64(val))); +#else + return MAKE_TCGV_TL(GET_TCGV_I32(tcg_const_local_i32(val))); +#endif +} #if TCG_TARGET_REG_BITS == 32 #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \ -- 1.7.7 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 3/4] tcg: Update TCGV_{UNUSED,EQUAL}() macros 2011-12-10 9:02 [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Andreas Färber 2011-12-10 9:02 ` [Qemu-devel] [PATCH 1/4] tcg: Introduce {MAKE,GET}_TCGV_TL macros Andreas Färber 2011-12-10 9:02 ` [Qemu-devel] [PATCH 2/4] tcg: Convert *_tl*() macros to inline functions Andreas Färber @ 2011-12-10 9:02 ` Andreas Färber 2011-12-10 9:02 ` [Qemu-devel] [PATCH 4/4] tcg: Allow to detect TCGv misuses Andreas Färber 2011-12-10 10:07 ` [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Peter Maydell 4 siblings, 0 replies; 16+ messages in thread From: Andreas Färber @ 2011-12-10 9:02 UTC (permalink / raw) To: qemu-devel; +Cc: Andreas Färber Switch them to use the new {MAKE,GET}_TCGV_TL() macros. Signed-off-by: Andreas Färber <andreas.faerber@web.de> --- tcg/tcg-op.h | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index e5c2e37..a6c3d5f 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2129,16 +2129,15 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #define TCGv TCGv_i32 #define MAKE_TCGV_TL(x) MAKE_TCGV_I32(x) #define GET_TCGV_TL(t) GET_TCGV_I32(t) -#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) -#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) #else #define TCGv TCGv_i64 #define MAKE_TCGV_TL(x) MAKE_TCGV_I64(x) #define GET_TCGV_TL(t) GET_TCGV_I64(t) -#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) -#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) #endif +#define TCGV_UNUSED(x) x = MAKE_TCGV_TL(-1) +#define TCGV_EQUAL(a, b) (GET_TCGV_TL(a) == GET_TCGV_TL(b)) + static inline TCGv tcg_temp_new(void) { #if TARGET_LONG_BITS == 32 -- 1.7.7 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 4/4] tcg: Allow to detect TCGv misuses 2011-12-10 9:02 [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Andreas Färber ` (2 preceding siblings ...) 2011-12-10 9:02 ` [Qemu-devel] [PATCH 3/4] tcg: Update TCGV_{UNUSED,EQUAL}() macros Andreas Färber @ 2011-12-10 9:02 ` Andreas Färber 2011-12-10 10:07 ` [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Peter Maydell 4 siblings, 0 replies; 16+ messages in thread From: Andreas Färber @ 2011-12-10 9:02 UTC (permalink / raw) To: qemu-devel; +Cc: Andreas Färber It's easy to omit _i32 somewhere if working on one 32-bit target, despite DEBUG_TCGV, because TCGv is simply aliased to TCGv_i32/i64. If DEBUG_TCGV_TL is defined, use a new struct TCGv with distinguished accessors to catch mixups. This cannot be done unconditionally for DEBUG_TCGV because some targets use TCGv and TCGv_i32/i64 interchangeably depending on TARGET_*. Signed-off-by: Andreas Färber <andreas.faerber@web.de> --- def-helper.h | 13 ++++++++----- tcg/tcg-op.h | 14 ++++++++++++++ tcg/tcg.h | 1 + 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/def-helper.h b/def-helper.h index 8a822c7..5be1110 100644 --- a/def-helper.h +++ b/def-helper.h @@ -22,8 +22,11 @@ #define GET_TCGV_i32 GET_TCGV_I32 #define GET_TCGV_i64 GET_TCGV_I64 +#define GET_TCGV_tl GET_TCGV_TL #define GET_TCGV_ptr GET_TCGV_PTR +#define TCGv_tl TCGv + /* Some types that make sense in C, but not for TCG. */ #define dh_alias_i32 i32 #define dh_alias_s32 i32 @@ -32,11 +35,7 @@ #define dh_alias_s64 i64 #define dh_alias_f32 i32 #define dh_alias_f64 i64 -#if TARGET_LONG_BITS == 32 -#define dh_alias_tl i32 -#else -#define dh_alias_tl i64 -#endif +#define dh_alias_tl tl #define dh_alias_ptr ptr #define dh_alias_void void #define dh_alias_env ptr @@ -60,24 +59,28 @@ #define dh_retvar_decl0_void void #define dh_retvar_decl0_i32 TCGv_i32 retval #define dh_retvar_decl0_i64 TCGv_i64 retval +#define dh_retvar_decl0_tl TCGv retval #define dh_retvar_decl0_ptr TCGv_ptr retval #define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t)) #define dh_retvar_decl_void #define dh_retvar_decl_i32 TCGv_i32 retval, #define dh_retvar_decl_i64 TCGv_i64 retval, +#define dh_retvar_decl_tl TCGv retval, #define dh_retvar_decl_ptr TCGv_ptr retval, #define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t)) #define dh_retvar_void TCG_CALL_DUMMY_ARG #define dh_retvar_i32 GET_TCGV_i32(retval) #define dh_retvar_i64 GET_TCGV_i64(retval) +#define dh_retvar_tl GET_TCGV_tl(retval) #define dh_retvar_ptr GET_TCGV_ptr(retval) #define dh_retvar(t) glue(dh_retvar_, dh_alias(t)) #define dh_is_64bit_void 0 #define dh_is_64bit_i32 0 #define dh_is_64bit_i64 1 +#define dh_is_64bit_tl (TARGET_LONG_BITS == 64) #define dh_is_64bit_ptr (TCG_TARGET_REG_BITS == 64) #define dh_is_64bit(t) glue(dh_is_64bit_, dh_alias(t)) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index a6c3d5f..d065e74 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2125,6 +2125,18 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #error must include QEMU headers #endif +#if defined(DEBUG_TCGV) && defined(DEBUG_TCGV_TL) + +typedef struct { + int itl; +} TCGv; + +#define MAKE_TCGV_TL(i) __extension__ \ + ({ TCGv make_tcgv_tmp = {i}; make_tcgv_tmp; }) +#define GET_TCGV_TL(t) ((t).itl) + +#else /* !DEBUG_TCGV_TL */ + #if TARGET_LONG_BITS == 32 #define TCGv TCGv_i32 #define MAKE_TCGV_TL(x) MAKE_TCGV_I32(x) @@ -2135,6 +2147,8 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #define GET_TCGV_TL(t) GET_TCGV_I64(t) #endif +#endif /* !DEBUG_TCGV_TL */ + #define TCGV_UNUSED(x) x = MAKE_TCGV_TL(-1) #define TCGV_EQUAL(a, b) (GET_TCGV_TL(a) == GET_TCGV_TL(b)) diff --git a/tcg/tcg.h b/tcg/tcg.h index 175000f..01bf74b 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -189,6 +189,7 @@ typedef tcg_target_ulong TCGArg; #ifdef CONFIG_DEBUG_TCG #define DEBUG_TCGV 1 +//#define DEBUG_TCGV_TL #endif #ifdef DEBUG_TCGV -- 1.7.7 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-10 9:02 [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Andreas Färber ` (3 preceding siblings ...) 2011-12-10 9:02 ` [Qemu-devel] [PATCH 4/4] tcg: Allow to detect TCGv misuses Andreas Färber @ 2011-12-10 10:07 ` Peter Maydell 2011-12-10 11:14 ` Andreas Färber 4 siblings, 1 reply; 16+ messages in thread From: Peter Maydell @ 2011-12-10 10:07 UTC (permalink / raw) To: Andreas Färber; +Cc: qemu-devel On 10 December 2011 09:02, Andreas Färber <andreas.faerber@web.de> wrote: > Working on 16- and 20-bit targets using TARGET_LONG_BITS == 32, I found it too > easy to accidentally use, e.g., tcg_temp_free() in place of tcg_temp_free_i32(). > In case of 78k0/rl78 it may not practically matter yet, but it complicates > going from a 32-bit target to 64 bits, as in the case of arm. > > This series refactors TCG code to allow using a dedicated struct for TCGv, > to make variable type mismatches show up as compilation errors. What mismatches does this catch that the existing debug code doesn't? I've always assumed that "TCGv is shorthand for either TCGv_32 or TCGv_64 depending on your target's word length" was a feature, not a bug. If we don't like that we should just drop TCGv completely, no? -- PMM ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-10 10:07 ` [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Peter Maydell @ 2011-12-10 11:14 ` Andreas Färber 2011-12-11 23:28 ` Paul Brook 0 siblings, 1 reply; 16+ messages in thread From: Andreas Färber @ 2011-12-10 11:14 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel Am 10.12.2011 11:07, schrieb Peter Maydell: > On 10 December 2011 09:02, Andreas Färber <andreas.faerber@web.de> wrote: >> Working on 16- and 20-bit targets using TARGET_LONG_BITS == 32, I found it too >> easy to accidentally use, e.g., tcg_temp_free() in place of tcg_temp_free_i32(). >> In case of 78k0/rl78 it may not practically matter yet, but it complicates >> going from a 32-bit target to 64 bits, as in the case of arm. >> >> This series refactors TCG code to allow using a dedicated struct for TCGv, >> to make variable type mismatches show up as compilation errors. > > What mismatches does this catch that the existing debug code doesn't? Cf. patch 4/4: TCGv tmp = tcg_temp_new_i32(); tcg_temp_free_i32(tmp); TCGv_i32 tmp2 = tcg_temp_new(); tcg_temp_free(tmp2); ...just to name four. Try compiling --target-list=arm-softmmu --enable-debug-tcg with my series and DEBUG_TCGV_TL uncommented, and you'll see for yourself. There's too many to mention and for me to actually fix. You'll have to deal with it for ARMv8 at some point and this series hopefully helps. > I've always assumed that "TCGv is shorthand for either TCGv_32 or TCGv_64 > depending on your target's word length" was a feature, not a bug. > If we don't like that we should just drop TCGv completely, no? No. TCGv is needed for what you describe. However, there's been nothing preventing you from using it when exactly that is *not* what you want. The only downside of my approach is that it cannot guess when you knowingly took a valid shortcut, so all shortcuts are discouraged. Andreas ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-10 11:14 ` Andreas Färber @ 2011-12-11 23:28 ` Paul Brook 2011-12-12 10:39 ` Andreas Färber 0 siblings, 1 reply; 16+ messages in thread From: Paul Brook @ 2011-12-11 23:28 UTC (permalink / raw) To: qemu-devel; +Cc: Peter Maydell, Andreas Färber > > What mismatches does this catch that the existing debug code doesn't? > > Cf. patch 4/4: > > TCGv tmp = tcg_temp_new_i32(); > tcg_temp_free_i32(tmp); > > TCGv_i32 tmp2 = tcg_temp_new(); > tcg_temp_free(tmp2); Why is this a problem? If TARGET_LONG_BITS==32 then tcg_temp_free and tcg_temp_free_i32 are synonyms, and everything is happy. If TARGET_LONG_BITS==64 then we already flag this as an error. > Try compiling --target-list=arm-softmmu --enable-debug-tcg with my > series and DEBUG_TCGV_TL uncommented, and you'll see for yourself. > There's too many to mention and for me to actually fix. You'll have to > deal with it for ARMv8 at some point and this series hopefully helps. That's exactly why I think this patch is a bad idea. If a target always has TARGET_LONG_BITS==32 then it doesn't matter if we mix TCGv and TCGv_i32. If a target has both 32-bit and 64-bit variants then at least one of these will already fail to build. I don't see how making both fail provides any benefit. As you say, whoever implements ARMv8 gets to fix all the mismatches when thay actually add the aarch64 support. Trying to make a 32-bit target "64-bit safe" without actually implementing the 64-bit target is a complete waste of time. You've almost no chance of getting it right. In some cases the correct answer will be to use 32-bit arithmetic, then sign/zero extend the result. In other cases the correct answer will be to perform word size arithmetic. Blindly picking one just makes the bugs harder to find later. If you're trying to add support for targets where the primary word size is neither 32 nor 64 then that's a completely different problem, and probably not one that's worth solving. In practice your port is going to end up using 64- bit arithmetic and explicitly compensating for the excess precision where necessary. Paul ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-11 23:28 ` Paul Brook @ 2011-12-12 10:39 ` Andreas Färber 2011-12-12 15:58 ` Paul Brook 0 siblings, 1 reply; 16+ messages in thread From: Andreas Färber @ 2011-12-12 10:39 UTC (permalink / raw) To: Paul Brook; +Cc: Peter Maydell, qemu-devel Am 12.12.2011 00:28, schrieb Paul Brook: >>> What mismatches does this catch that the existing debug code doesn't? >> >> Cf. patch 4/4: >> >> TCGv tmp = tcg_temp_new_i32(); >> tcg_temp_free_i32(tmp); >> >> TCGv_i32 tmp2 = tcg_temp_new(); >> tcg_temp_free(tmp2); > > Why is this a problem? If TARGET_LONG_BITS==32 then tcg_temp_free and > tcg_temp_free_i32 are synonyms, and everything is happy. > > If TARGET_LONG_BITS==64 then we already flag this as an error. > >> Try compiling --target-list=arm-softmmu --enable-debug-tcg with my >> series and DEBUG_TCGV_TL uncommented, and you'll see for yourself. >> There's too many to mention and for me to actually fix. You'll have to >> deal with it for ARMv8 at some point and this series hopefully helps. > > That's exactly why I think this patch is a bad idea. > > If a target always has TARGET_LONG_BITS==32 then it doesn't matter if we mix > TCGv and TCGv_i32. To me and my perfectionism it does matter. This is not about fixing some user-visible runtime bug, it's about making the developer (me) aware of unintended type mixups. > Trying to make a 32-bit target "64-bit safe" without actually implementing the > 64-bit target is a complete waste of time. That's where we disagree. I rather do things right from the start than leaving the cleanup work to someone else later on. > You've almost no chance of getting > it right. In some cases the correct answer will be to use 32-bit arithmetic, > then sign/zero extend the result. In other cases the correct answer will be to > perform word size arithmetic. Blindly picking one just makes the bugs harder > to find later. This series picks nothing blindly. It provides an optional facility for the developer to be made aware of uses of tl where i32/i64 was intended (or vice versa), nothing changes at runtime. Whether and in which way the developer addresses the issues shown that way is up to the developer, and as any line added to a new target must be decided on a case-by-case basis. For me the most annoying issue was that tcg_gen_qemu_{ld,st}* needs TCGv. > If you're trying to add support for targets where the primary word size is > neither 32 nor 64 then that's a completely different problem, and probably not > one that's worth solving. In practice your port is going to end up using 64- > bit arithmetic and explicitly compensating for the excess precision where > necessary. That's a different issue and not being addressed here. My point was that I have an inheritance hierarchy where (as opposed to, e.g., ppc and ppc64) both end up as TARGET_LONG_BITS==32, so I do not get a check for free by compiling both, and I do not want to introduce an artificial TARGET_LONG_BITS==64 architecture just to check that my tl==i32 target code is free of typos. Same issue if you pick only --target-list=<some>-softmmu BTW. Just like with softfloat [u]int16 etc. types it's just too easy to forget _t somewhere (here: _i32) and to end up with a type you don't want. If you have a better proposal how to introduce the checks I want, please let us hear it. If no one has, I don't see how this series would hurt (1-3 refactoring, 4 not enabled by default) while providing useful new debug facilities to developers of new targets. Andreas ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-12 10:39 ` Andreas Färber @ 2011-12-12 15:58 ` Paul Brook 2011-12-13 12:43 ` Andreas Färber 2011-12-13 13:11 ` Andreas Färber 0 siblings, 2 replies; 16+ messages in thread From: Paul Brook @ 2011-12-12 15:58 UTC (permalink / raw) To: Andreas Färber; +Cc: Peter Maydell, qemu-devel > > Trying to make a 32-bit target "64-bit safe" without actually > > implementing the 64-bit target is a complete waste of time. > > That's where we disagree. I rather do things right from the start than > leaving the cleanup work to someone else later on. > > > You've almost no chance of getting > > it right. In some cases the correct answer will be to use 32-bit > > arithmetic, then sign/zero extend the result. In other cases the correct > > answer will be to perform word size arithmetic. Blindly picking one > > just makes the bugs harder to find later. > > This series picks nothing blindly. Sure it does - or at least it will when you get to ARM and m68k[1]. The whole point of your patch is to force developers to pick between an address sized value and a 32-bit value. On a 32-bit target these are the same thing. Not only are they the same thing, but most of the time the architecture doesn't even have the concept that they may be different. Only when you introduce a variant with 64-bit addresses does the distinction become meaningful. At that point they're actually different, and are trivially detected by the existing checks. Ther are three ways to resolve a mismatch: - Change everything to TCGv_i32. - Change everything to TCGv. - Add an explicit extension/truncation (compiles to no-op on 32-bit targets). There's no way of the developer of a 32-bit architecture to know which of these a [hypothetical future] 64-bit architecture will require. The fact they you've been forced to pick one (rather then leave the mismatch for the 64-bit porter to resolve) actually makes bugs harder to find. > For me the most annoying issue was that tcg_gen_qemu_{ld,st}* needs TCGv. You mean the value transferred is always TCGv sized, so ld32u requires an additional truncation before doing 32-bit arithmetic? Fixing that is completely independent of making TCGv a separate type. The whole point of TCGv is that it's an address sized value, so is the only real option for the address. Constructing an address for a different sized value requires a target specific sign/szero extension or truncation/overflow check. > > If you're trying to add support for targets where the primary word size > > is neither 32 nor 64 then that's a completely different problem, and > > probably not one that's worth solving. In practice your port is going > > to end up using 64- bit arithmetic and explicitly compensating for the > > excess precision where necessary. > > That's a different issue and not being addressed here. Good. > My point was that I have an inheritance hierarchy where (as opposed to, > e.g., ppc and ppc64) both end up as TARGET_LONG_BITS==32, so I do not > get a check for free by compiling both, and I do not want to introduce > an artificial TARGET_LONG_BITS==64 architecture just to check that my > tl==i32 target code is free of typos. Huh? Now I'm completely confused. If all your targets have T_L_B==32 how can mixing TCGv and TCGV_i32 be wrong? How do you know which of the 3 alternatives above is the right answer? > Same issue if you pick only --target-list=<some>-softmmu BTW. If you're only building a small subset of targets then clearly you won't see errors in the targets you omitted. The only sane answer is to make sure you build (and preferably test) all the targets you have effected. This is the same reason I object to code that is disabled by default. If it isn't at least being built by the majority of developers (or at least any working in related areas) then it's going to bitrot rapidly, and probably won't work when someone does decide to turn it on. > Just like with softfloat [u]int16 etc. types it's just too easy to > forget _t somewhere (here: _i32) and to end up with a type you don't want. I don't see how that is relevant. TCGv (aka target_ulong) is a synonym for either TCGv_i32 (uint32_t) or TCGv_i64 (uint64_t). If this is not true then we're completely screwed. > If you have a better proposal how to introduce the checks I want, please > let us hear it. I still don't understand how your additional restructions are ever useful. Please give an example of an actual error your checks will catch. Paul [1] m68k may never have a 64-bit variant, but ARM is a good example of a qemu target that is currently 32-bit but will grow a 64-bit variant in the not too distant future. ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-12 15:58 ` Paul Brook @ 2011-12-13 12:43 ` Andreas Färber 2011-12-13 16:26 ` Paul Brook 2011-12-13 13:11 ` Andreas Färber 1 sibling, 1 reply; 16+ messages in thread From: Andreas Färber @ 2011-12-13 12:43 UTC (permalink / raw) To: Paul Brook; +Cc: Peter Maydell, qemu-devel Am 12.12.2011 16:58, schrieb Paul Brook: >>> Trying to make a 32-bit target "64-bit safe" without actually >>> implementing the 64-bit target is a complete waste of time. >> >> That's where we disagree. I rather do things right from the start than >> leaving the cleanup work to someone else later on. >> >>> You've almost no chance of getting >>> it right. In some cases the correct answer will be to use 32-bit >>> arithmetic, then sign/zero extend the result. In other cases the correct >>> answer will be to perform word size arithmetic. Blindly picking one >>> just makes the bugs harder to find later. >> >> This series picks nothing blindly. > > Sure it does [snip] No, start by reading the git summary. These four patches don't touch target-* at all. This is intentionally NOT some Coccinelle script running wild doing refactorings. That's what I would call "blindly". > Ther are three ways to resolve a mismatch: > - Change everything to TCGv_i32. > - Change everything to TCGv. > - Add an explicit extension/truncation (compiles to no-op on 32-bit targets). > > There's no way of the developer of a 32-bit architecture to know [snip] Again, that's where we disagree: The whole point of TCGv and tl is to have variable-sized operations scaling with target_long. Thus, using them for fixed-size i32 or i64 operations is a semantic error by definition. Whether or not an i64 target exists. And I certainly don't want to knowingly introduce semantic errors in my new code just so that at another time someone else can use that to review a 64-bit port. That's just plain stupid. As the developer I must know what semantics I am implementing for my target. Note that the three choices are independent of this series, same holds without. The difference is, my series offers a way to *flag* cases where this has been ignored. >> If you have a better proposal how to introduce the checks I want, please >> let us hear it. > I still don't understand how your additional restructions are ever useful. > Please give an example of an actual error your checks will catch. My stated requirement is that I want to detect ALL uses of TCGv_i32 with tl functions and all uses of TCGv with i32 functions, be it an error or a warning. Whether or not such consistency seems useful to you. I have already given four examples to Peter, that you quoted previously. Consider a uint32_t 8-bit status register on a 20-bit architecture - it never scales to i64 so I know that TCGv/tl is definitely wrong! Either point out something that's technically wrong with these patches and I'll gladly fix it, or, again, propose a constructive solution. Reappearing after a year and destructively objecting to patches is something we've been through before. Thanks, Andreas ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-13 12:43 ` Andreas Färber @ 2011-12-13 16:26 ` Paul Brook 2011-12-14 11:41 ` Andreas Färber 0 siblings, 1 reply; 16+ messages in thread From: Paul Brook @ 2011-12-13 16:26 UTC (permalink / raw) To: Andreas Färber; +Cc: Peter Maydell, qemu-devel > >>> You've almost no chance of getting > >>> it right. In some cases the correct answer will be to use 32-bit > >>> arithmetic, then sign/zero extend the result. In other cases the > >>> correct answer will be to perform word size arithmetic. Blindly > >>> picking one just makes the bugs harder to find later. > >> > >> This series picks nothing blindly. > > > > Sure it does > > No, start by reading the git summary. These four patches don't touch > target-* at all. > > This is intentionally NOT some Coccinelle script running wild doing > refactorings. That's what I would call "blindly". IIUC these four patches do precicely nothing. They simply add a pile of dead code. If you don't intent on making these checks pass for all targets, and enabling them for at least debug builds then I strongly object. These checks will bitrot rapidly if not routinely enforced. > > Ther are three ways to resolve a mismatch: > > - Change everything to TCGv_i32. > > - Change everything to TCGv. > > - Add an explicit extension/truncation (compiles to no-op on 32-bit > > targets). > > > > There's no way of the developer of a 32-bit architecture to know > > Again, that's where we disagree: > > The whole point of TCGv and tl is to have variable-sized operations > scaling with target_long. So you're claiming that a 32-bit only target can somehow distinguish between a 32-bit value, and a value that is architecturally defined to always be 32-bit. I don't believe any useful determination can be made in this case. For targets with different target_ulong variants simply building those variants with the existing checks will already highlight any mismatches. AFAICS the best you can do is say that 32-bit only targets should never use TCGv. While that might be a nice idea in theory, the opposite is true for the current code base. This is because the original TCG implementation did not do any static typing, i.e. everything was TCGv. It was only later that I gave TCG variables a static size. I see no practical harm from leaving that as-is. Introducing a substantial amount of churn and extra complication to achieve a purely theoretical goal is a bad idea. > I have already given four examples to Peter, that you quoted previously. The examples I quoted where where TCGv and TCGv_i32 were mixed, but I don't see how any of those could possibly cause incorrect behovior. If the two were ever different then this would already fail to compile. So I'll ask again: Please give a worked example of a programming error that is caught by your new restrictions. Feel free to use hypothetical code and/or targets. Paul ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-13 16:26 ` Paul Brook @ 2011-12-14 11:41 ` Andreas Färber 0 siblings, 0 replies; 16+ messages in thread From: Andreas Färber @ 2011-12-14 11:41 UTC (permalink / raw) To: Paul Brook; +Cc: Blue Swirl, Peter Maydell, qemu-devel, Stefan Weil Am 13.12.2011 17:26, schrieb Paul Brook: >>>>> You've almost no chance of getting >>>>> it right. In some cases the correct answer will be to use 32-bit >>>>> arithmetic, then sign/zero extend the result. In other cases the >>>>> correct answer will be to perform word size arithmetic. Blindly >>>>> picking one just makes the bugs harder to find later. >>>> >>>> This series picks nothing blindly. >>> >>> Sure it does >> >> No, start by reading the git summary. These four patches don't touch >> target-* at all. >> >> This is intentionally NOT some Coccinelle script running wild doing >> refactorings. That's what I would call "blindly". > > IIUC these four patches do precicely nothing. No, only patch 4/4 does nothing if not enabled. Patches 1-3 are actively used by all targets. And specifically, patch 2/4 is highly likely to break if kept out-of-tree when someone adds tcg_gen_somethingclever_tl(). Blue (cc'ed) has been asking me to convert macros into inline functions all over OpenBIOS with no practical runtime change, so the overall change does not seem Wrong(tm), just a matter of taste and (here) allowing additional features. Is it the MAKE+GET combo that disturbs you there? If so, do you have a better suggestion? TGCV_Ixx_TO_TL(foo) that can compile to (foo) by default? >>> Ther are three ways to resolve a mismatch: >>> - Change everything to TCGv_i32. >>> - Change everything to TCGv. >>> - Add an explicit extension/truncation (compiles to no-op on 32-bit >>> targets). >>> >>> There's no way of the developer of a 32-bit architecture to know >> >> Again, that's where we disagree: >> >> The whole point of TCGv and tl is to have variable-sized operations >> scaling with target_long. > > So you're claiming that a 32-bit only target can somehow distinguish between a > 32-bit value, and a value that is architecturally defined to always be 32-bit. > I don't believe any useful determination can be made in this case. > > For targets with different target_ulong variants simply building those > variants with the existing checks will already highlight any mismatches. > > AFAICS the best you can do is say that 32-bit only targets should never use > TCGv. While that might be a nice idea in theory, the opposite is true for the > current code base. This is because the original TCG implementation did not do > any static typing, i.e. everything was TCGv. It was only later that I gave > TCG variables a static size. I see no practical harm from leaving that as-is. > Introducing a substantial amount of churn and extra complication to achieve a > purely theoretical goal is a bad idea. > >> I have already given four examples to Peter, that you quoted previously. > > The examples I quoted where where TCGv and TCGv_i32 were mixed, but I don't > see how any of those could possibly cause incorrect behovior. If the two were > ever different then this would already fail to compile. > > So I'll ask again: Please give a worked example of a programming error that is > caught by your new restrictions. Feel free to use hypothetical code and/or > targets. We don't seem to be getting anywhere with this discussion... Quote: "This is not about fixing some user-visible runtime bug, it's about making the developer (me) aware of unintended type mixups." Once again, there are targets - RL78, 78K0, 78K0S, 78K0R, STM8, who knows how many others - that have registers of width < 32 that *never* scale with physical address width. This I know for sure as the developer. Thus, using tl functions that will scale to 64 bits is undoubtedly Wrong(tm) and I strive to get my new code Right(tm). For example, the TARGET_78K0 / TARGET_RL78 Processor Status Word is 8 bits, always (same for the ST7 / STM8 Accumulator and Condition Code Register). Therefore i32 as our lowest supported temporary size. The PSW contains a two-bit GPR bank number, still i32 once extracted. I use it to calculate a target address for tcg_gen_qemu_{ld,st}*(), which must be TCGv, so may scale to 64 bits. So I must be careful about TCGv and TCGv_i32 a) for the signature of my static helper functions, b) for the per-instruction temporary variables and c) for the TCG functions called with those variables. Whether or not you understand this forward-looking desire of mine, for the current (not historic!) code base I would theoretically like some warning mechanism like: #if TCGv debug feature desired for this target #if TCGv argument was passed a TCGv_i32 variable then #warning Ouch, expected TCGv but got a TCGv_i32. #endif #endif In practice, I don't see any other way than making TCGv and TCGv_i32 incompatible with each other by using different structs with different member names, like TCGv_i32/i64 do, which - yes, here unnecessarily - then leads to a compilation error even with --disable-werror. Neither warning nor error should be enabled on the default, optimized build IMO (just like --enable-debug-tcg isn't, and that we have in-tree despite occasional --enable-debug-tcg build breakages that Stefan W. and others have volunteered to fix from time to time). Me, I don't see any reason to activate this for existing m68k, so we could easily have this special debug #define only enabled for select targets (mine) by configure iff --enable-debug-tcg is passed. No existing target would break that way and I of course intend to maintain this feature. Now, do you have a better solution how to do this or not? If yes, please share. If not, do you have a suggestion how to change my patches so that prerequisite parts thereof become acceptable for you or any other maintainer to apply? Anything else - repeating that this doesn't make a difference for your favorite targets, asking me for examples over and over - doesn't help. Thanks in advance, Andreas ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-12 15:58 ` Paul Brook 2011-12-13 12:43 ` Andreas Färber @ 2011-12-13 13:11 ` Andreas Färber 2011-12-13 16:23 ` Paul Brook 1 sibling, 1 reply; 16+ messages in thread From: Andreas Färber @ 2011-12-13 13:11 UTC (permalink / raw) To: Paul Brook; +Cc: Peter Maydell, qemu-devel Am 12.12.2011 16:58, schrieb Paul Brook: >> For me the most annoying issue was that tcg_gen_qemu_{ld,st}* needs TCGv. > > You mean the value transferred is always TCGv sized, so ld32u requires an > additional truncation before doing 32-bit arithmetic? Fixing that is > completely independent of making TCGv a separate type. tcg_gen_qemu_{ld,st} (guest) differs from tcg_gen_{ld,st} (host) in that they require a TCGv ret/arg (all use TCGv addr). I.e., to read an 8-bit memory-mapped register on a 64-bit target with tcg_gen_qemu_ld8u we need a TCGv temporary and trunc to i32 afterwards (smallest currently available variable size) or unnecessarily blow up storage size to target_long/TCGv everywhere. So, yes, adding an _i32 version may make sense, to at least encapsulate it at TCG level. And without my patches I might have not noticed this design flaw. :) Andreas ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv 2011-12-13 13:11 ` Andreas Färber @ 2011-12-13 16:23 ` Paul Brook 0 siblings, 0 replies; 16+ messages in thread From: Paul Brook @ 2011-12-13 16:23 UTC (permalink / raw) To: Andreas Färber; +Cc: Peter Maydell, qemu-devel > Am 12.12.2011 16:58, schrieb Paul Brook: > >> For me the most annoying issue was that tcg_gen_qemu_{ld,st}* needs > >> TCGv. > > > > You mean the value transferred is always TCGv sized, so ld32u requires an > > additional truncation before doing 32-bit arithmetic? Fixing that is > > completely independent of making TCGv a separate type. > > tcg_gen_qemu_{ld,st} (guest) differs from tcg_gen_{ld,st} (host) in that > they require a TCGv ret/arg (all use TCGv addr). I.e., to read an 8-bit > memory-mapped register on a 64-bit target with tcg_gen_qemu_ld8u we need > a TCGv temporary and trunc to i32 afterwards (smallest currently > available variable size) or unnecessarily blow up storage size to > target_long/TCGv everywhere. > > So, yes, adding an _i32 version may make sense, to at least encapsulate > it at TCG level. > > And without my patches I might have not noticed this design flaw. :) This is purely an optimization issue. If you're concerned about cases where TCG generates dumb code then this is probably the least of your problems. If you omit the truncation then the build will fail. My guess is that in many cases we also manage to optimize away the worst of the redundant extension/truncation. Paul ^ permalink raw reply [flat|nested] 16+ messages in thread
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Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
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2011-12-10 9:02 [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Andreas Färber
2011-12-10 9:02 ` [Qemu-devel] [PATCH 1/4] tcg: Introduce {MAKE,GET}_TCGV_TL macros Andreas Färber
2011-12-10 9:02 ` [Qemu-devel] [PATCH 2/4] tcg: Convert *_tl*() macros to inline functions Andreas Färber
2011-12-10 21:06 ` [Qemu-devel] [PATCH v2] " Andreas Färber
2011-12-10 9:02 ` [Qemu-devel] [PATCH 3/4] tcg: Update TCGV_{UNUSED,EQUAL}() macros Andreas Färber
2011-12-10 9:02 ` [Qemu-devel] [PATCH 4/4] tcg: Allow to detect TCGv misuses Andreas Färber
2011-12-10 10:07 ` [Qemu-devel] [PATCH 0/4] tcg: Add debug facilities for TCGv Peter Maydell
2011-12-10 11:14 ` Andreas Färber
2011-12-11 23:28 ` Paul Brook
2011-12-12 10:39 ` Andreas Färber
2011-12-12 15:58 ` Paul Brook
2011-12-13 12:43 ` Andreas Färber
2011-12-13 16:26 ` Paul Brook
2011-12-14 11:41 ` Andreas Färber
2011-12-13 13:11 ` Andreas Färber
2011-12-13 16:23 ` Paul Brook
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