From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([140.186.70.92]:41047)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1RasGe-0003qw-5M
	for qemu-devel@nongnu.org; Wed, 14 Dec 2011 12:05:24 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1RasGY-0005Jr-Bg
	for qemu-devel@nongnu.org; Wed, 14 Dec 2011 12:05:20 -0500
Received: from mail-qw0-f52.google.com ([209.85.216.52]:44648)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1RasGY-0005Jm-8B
	for qemu-devel@nongnu.org; Wed, 14 Dec 2011 12:05:14 -0500
Received: by qadc11 with SMTP id c11so678761qad.4
	for <qemu-devel@nongnu.org>; Wed, 14 Dec 2011 09:05:13 -0800 (PST)
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <4EE8D745.7080908@twiddle.net>
Date: Wed, 14 Dec 2011 09:05:09 -0800
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1323321912-15922-1-git-send-email-khansa@kics.edu.pk>
	<1323321912-15922-3-git-send-email-khansa@kics.edu.pk>
	<4EE15075.6060208@web.de>
In-Reply-To: <4EE15075.6060208@web.de>
Content-Type: text/plain; charset=ISO-8859-15
Content-Transfer-Encoding: 8bit
Subject: Re: [Qemu-devel] [PATCH 2/3] target-mips:enabling of 64 bit user
 mode and floating point operations MIPS_HFLAG_UX is included in env->hflags
 so that the address computation for LD instruction does not treated as 32
 bit code see gen_op_addr_add() in translate.c
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: =?ISO-8859-15?Q?Andreas_F=E4rber?= <andreas.faerber@web.de>
Cc: peter.maydell@linaro.org, Nathan Froyd <froydnj@codesourcery.com>, Stefan Weil <sw@weilnetz.de>, riku.voipio@iki.fi, qemu-devel@nongnu.org, khansa@kics.edu.pk, aurelien@aurel32.net

On 12/08/2011 04:04 PM, Andreas Färber wrote:
>> > +    /* if cpu has FPU, MIPS_HFLAG_F64 must be included in env->hflags
>> > +       so that floating point operations can be emulated */
>> > +    env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
>> >      if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
>> >          env->hflags |= MIPS_HFLAG_F64;
>> >      }
> Nack. env->active_fpu.fcr0 gets initialized in translate_init.c based on
> cpu_model->CR1_fcr0, where FCR0_F64 is set only for 24Kf, 34Kf,
> MIPS64R2-generic. TARGET_ABI_MIPSN64 linux-user defaults to 20Kc. So it
> seems to rather be an issue of using the right -cpu parameter or
> changing the default for n64. [cc'ing Nathan, who introduced the if]

That said, there's still something missing, e.g. MIPS_HFLAG_COP1X.
My first guess is simply

    if (env->insn_flags & (ISA_MIPS32 | ISA_MIPS4)) {
        env->hflags |= MIPS_HFLAG_COP1X;
    }

immediately after this MIPS64 hunk.


r~