From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47468) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd56G-0005dT-61 for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:11:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rd569-00065x-Re for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:11:44 -0500 Received: from smtp191.dfw.emailsrvr.com ([67.192.241.191]:51183) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd569-00065l-KB for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:11:37 -0500 Message-ID: <4EF0DDEB.40302@calxeda.com> Date: Tue, 20 Dec 2011 13:11:39 -0600 From: Mark Langsdorf MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 4/9] arm: add dummy gic security registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, paul@codesourcery.com From: Rob Herring Signed-off-by: Rob Herring Signed-off-by: Mark Langsdorf --- hw/arm_gic.c | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 9b52119..5974c2f 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -274,7 +274,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) cpu = gic_get_current_cpu(); cm = 1 << cpu; - if (offset < 0x100) { + if (offset < 0x80) { #ifndef NVIC if (offset == 0) return s->enabled; @@ -284,6 +284,9 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) return 0; #endif goto bad_reg; + } else if (offset < 0x100) { + /* Interrupt Security */ + return 0; } else if (offset < 0x200) { /* Interrupt Set/Clear Enable. */ if (offset < 0x180) @@ -404,7 +407,7 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, int cpu; cpu = gic_get_current_cpu(); - if (offset < 0x100) { + if (offset < 0x80) { #ifdef NVIC goto bad_reg; #else @@ -417,6 +420,9 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, goto bad_reg; } #endif + } else if (offset < 0x100) { + /* Interrupt Security Registers */ + /* ignore */ } else if (offset < 0x180) { /* Interrupt Set Enable. */ irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; -- 1.7.5.4