From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:49186) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rdi6l-0002vT-L5 for qemu-devel@nongnu.org; Thu, 22 Dec 2011 07:50:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rdi6f-0005fM-Rq for qemu-devel@nongnu.org; Thu, 22 Dec 2011 07:50:51 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:34268) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rdi6f-0005f6-I0 for qemu-devel@nongnu.org; Thu, 22 Dec 2011 07:50:45 -0500 Received: from euspt1 (mailout2.w1.samsung.com [210.118.77.12]) by mailout2.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTP id <0LWL00FGYVOI4R@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Thu, 22 Dec 2011 12:50:42 +0000 (GMT) Received: from [106.109.8.48] by spt1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LWL006U2VOIHO@spt1.w1.samsung.com> for qemu-devel@nongnu.org; Thu, 22 Dec 2011 12:50:42 +0000 (GMT) Date: Thu, 22 Dec 2011 16:50:40 +0400 From: Evgeny Voevodin In-reply-to: Message-id: <4EF327A0.8060300@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=UTF-8; format=flowed Content-transfer-encoding: 7BIT References: <1324295617-5798-1-git-send-email-e.voevodin@samsung.com> <1324295617-5798-5-git-send-email-e.voevodin@samsung.com> <4EF1F681.7090805@samsung.com> <4EF2D636.6000609@samsung.com> Subject: Re: [Qemu-devel] [PATCH v4 04/11] ARM: exynos4210: IRQ subsystem support. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: m.kozlov@samsung.com, qemu-devel@nongnu.org, d.solodkiy@samsung.com On 12/22/2011 04:30 PM, Peter Maydell wrote: > On 22 December 2011 07:03, Evgeny Voevodin wrote: >> Second GIC (external) is represented as "exynos4210.gic" with splitted >> mapping for CPU (0x10480000) and Distributer (0x10490000) (we used >> arm_gic.c availability to split CPU and Distributer memories). >> >> The reason for creation of this device with it's own read/write functions >> is: >> >> CPU and Distributer registers which are banked per SMP Core in internal GIC >> are not banked in external GIC and their offsets could not be used as is >> with arm_gic.c. >> External GIC registers in comparison to Internal GIC registers are moved >> from base by offset n * 0x8000 for each SMP Core, where n is SMP Core index. > Right, so just map each of the memory regions arm_gic exposes for > core 0, core 1, ... to these addresses, and don't map the memory > region corresponding to "CPU interface for this core" at all. > > -- PMM > Do you mean to use s->gic.cpuiomem[NCPU+1] as in a9mpcore.c a9mp_priv_init() done? What should we use if we need the same for distributor which is represented as gic.iomem? Extend distributor in the same way? -- Kind regards, Evgeny Voevodin, Leading Software Engineer, ASWG, Moscow R&D center, Samsung Electronics e-mail: e.voevodin@samsung.com