From: Rob Herring <rob.herring@calxeda.com>
To: Mark Langsdorf <mark.langsdorf@calxeda.com>
Cc: kwolf@redhat.com, peter.maydell@linaro.org,
qemu-devel@nongnu.org, paul@codesourcery.com
Subject: Re: [Qemu-devel] [PATCH 9/9] arm: increase a9mp interrupts to 160
Date: Fri, 23 Dec 2011 18:54:34 -0600 [thread overview]
Message-ID: <4EF522CA.4040106@calxeda.com> (raw)
In-Reply-To: <1324578014-24746-10-git-send-email-mark.langsdorf@calxeda.com>
Mark,
On 12/22/2011 12:20 PM, Mark Langsdorf wrote:
> From: Rob Herring <rob.herring@calxeda.com>
>
> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
> ---
> hw/a9mpcore.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
> index 875ae98..93b0498 100644
> --- a/hw/a9mpcore.c
> +++ b/hw/a9mpcore.c
> @@ -13,7 +13,7 @@
> /* Configuration for arm_gic.c:
> * number of external IRQ lines, max number of CPUs, how to ID current CPU
> */
> -#define GIC_NIRQ 96
> +#define GIC_NIRQ 160
> #define NCPU 4
This needs to be run-time. The value gets put in a register and read by
the OS. It breaks platforms expecting 96 irqs.
Rob
next prev parent reply other threads:[~2011-12-24 0:54 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-22 18:20 [Qemu-devel] [PATCH v2 0/9] various ARM fixes Mark Langsdorf
2011-12-22 18:20 ` [Qemu-devel] [PATCH v2 1/9] arm: add missing scu registers Mark Langsdorf
2011-12-24 0:23 ` Peter Maydell
2011-12-22 18:20 ` [Qemu-devel] [PATCH v2 2/9] arm: Set frequencies for arm_timer Mark Langsdorf
2011-12-24 0:26 ` Peter Maydell
2011-12-24 9:19 ` Andreas Färber
2011-12-22 18:20 ` [Qemu-devel] [PATCH v2 3/9] arm: add dummy v7 cp15 config_base_register Mark Langsdorf
2011-12-24 0:30 ` Peter Maydell
2011-12-22 18:20 ` [Qemu-devel] [PATCH v2 4/9] arm: add dummy gic security registers Mark Langsdorf
2011-12-24 0:32 ` Peter Maydell
2011-12-22 18:20 ` [Qemu-devel] [PATCH 5/9] ahci: convert ahci_reset to use AHCIState Mark Langsdorf
2011-12-24 0:35 ` Peter Maydell
2011-12-22 18:20 ` [Qemu-devel] [PATCH 6/9] ahci: add support for non-PCI based controllers Mark Langsdorf
2011-12-24 0:39 ` Peter Maydell
2011-12-22 18:20 ` [Qemu-devel] [PATCH v2 7/9] add L2x0/PL310 cache controller device Mark Langsdorf
2011-12-24 0:53 ` Peter Maydell
2011-12-22 18:20 ` [Qemu-devel] [PATCH v2 8/9] Add xgmac ethernet model Mark Langsdorf
2011-12-22 18:20 ` [Qemu-devel] [PATCH 9/9] arm: increase a9mp interrupts to 160 Mark Langsdorf
2011-12-24 0:54 ` Rob Herring [this message]
2011-12-24 1:10 ` Peter Maydell
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