From: Mark Langsdorf <mark.langsdorf@calxeda.com>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v6 1/1] arm: add dummy v7 cp15 registers
Date: Wed, 04 Jan 2012 12:23:00 -0600 [thread overview]
Message-ID: <4F049904.8060006@calxeda.com> (raw)
In-Reply-To: <CAFEAcA8q0iFOAH4NMCEkj0hJoh_LgV7sFe0wdyQaxZDieR6Vhg@mail.gmail.com>
On 01/04/2012 11:50 AM, Peter Maydell wrote:
> On 4 January 2012 16:53, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
>> + } else if ((op1 == 0) && (op2 == 0)) {
>> + /* power_control should be set to maximum latency. Again,
>> + default to 0 and set by private hook */
>> + return env->cp15.c15_power_control;
>> + }
>
> This one's read-write, which means it needs (a) support in set_cp15
> (b) save/load support.
Okay.
> You also need to implement the diagnostic register c15,c0,0,1
> otherwise Linux won't boot when it tries to run this code:
> http://lxr.linux.no/#linux+v3.1.7/arch/arm/mm/proc-v7.S#L345
> I suggest that should be implemented as reads-as-written. (Again, will
> need save/load
> support.) Ditto for the power diagnostic control register c15,c0,0,2, as used in
> this patch: http://www.spinics.net/lists/arm-kernel/msg115817.html
I'm handling all the c15 registers listed on p 4-11 of the Cortex-A9
r3p0 TRM. Would you please give me a reference for these other two
registers? I'm not seeing them. Thanks.
--Mark
next prev parent reply other threads:[~2012-01-04 18:22 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-29 16:19 [Qemu-devel] [PATCH v5 0/7] various ARM fixes for Calxeda Highbank Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 1/7] arm: add missing scu registers Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 2/7] arm: Set frequencies for arm_timer Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 3/7] arm: add dummy v7 cp15 config_base_register Mark Langsdorf
2012-01-04 14:32 ` Peter Maydell
2012-01-04 16:32 ` Mark Langsdorf
2012-01-04 16:47 ` Peter Maydell
2012-01-04 16:53 ` [Qemu-devel] [PATCH v6 1/1] arm: add dummy v7 cp15 registers Mark Langsdorf
2012-01-04 17:50 ` Peter Maydell
2012-01-04 18:23 ` Mark Langsdorf [this message]
2012-01-04 19:07 ` [Qemu-devel] [PATCH v7] " Mark Langsdorf
2012-01-04 23:50 ` Peter Maydell
2012-01-05 0:14 ` [Qemu-devel] [PATCH v8] " Mark Langsdorf
2012-01-05 0:22 ` Peter Maydell
2012-01-05 0:54 ` Mark Langsdorf
2012-01-05 8:36 ` Peter Maydell
2012-01-05 13:16 ` [Qemu-devel] [PATCH v9] " Mark Langsdorf
2012-01-05 15:33 ` Peter Maydell
2012-01-05 15:34 ` Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 4/7] arm: add dummy gic security registers Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 5/5] add L2x0/PL310 cache controller device Mark Langsdorf
2012-01-04 13:29 ` Peter Maydell
2012-06-07 13:45 ` Andreas Färber
2012-06-07 14:21 ` Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 6/7] Add xgmac ethernet model Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 7/7] arm: make the number of GIC interrupts configurable Mark Langsdorf
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