From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:41698) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RiVU7-0008Nk-9Z for qemu-devel@nongnu.org; Wed, 04 Jan 2012 13:22:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RiVU5-0000pB-Uh for qemu-devel@nongnu.org; Wed, 04 Jan 2012 13:22:47 -0500 Received: from smtp191.dfw.emailsrvr.com ([67.192.241.191]:33654) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RiVU5-0000p5-QK for qemu-devel@nongnu.org; Wed, 04 Jan 2012 13:22:45 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp19.relay.dfw1a.emailsrvr.com (SMTP Server) with ESMTP id 2280A3C81BB for ; Wed, 4 Jan 2012 13:22:45 -0500 (EST) Received: by smtp19.relay.dfw1a.emailsrvr.com (Authenticated sender: mark.langsdorf-AT-calxeda.com) with ESMTPSA id 0C2B13C8BBC for ; Wed, 4 Jan 2012 13:22:44 -0500 (EST) Message-ID: <4F049904.8060006@calxeda.com> Date: Wed, 04 Jan 2012 12:23:00 -0600 From: Mark Langsdorf MIME-Version: 1.0 References: <1325695989-4202-1-git-send-email-mark.langsdorf@calxeda.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v6 1/1] arm: add dummy v7 cp15 registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 01/04/2012 11:50 AM, Peter Maydell wrote: > On 4 January 2012 16:53, Mark Langsdorf wrote: >> + } else if ((op1 == 0) && (op2 == 0)) { >> + /* power_control should be set to maximum latency. Again, >> + default to 0 and set by private hook */ >> + return env->cp15.c15_power_control; >> + } > > This one's read-write, which means it needs (a) support in set_cp15 > (b) save/load support. Okay. > You also need to implement the diagnostic register c15,c0,0,1 > otherwise Linux won't boot when it tries to run this code: > http://lxr.linux.no/#linux+v3.1.7/arch/arm/mm/proc-v7.S#L345 > I suggest that should be implemented as reads-as-written. (Again, will > need save/load > support.) Ditto for the power diagnostic control register c15,c0,0,2, as used in > this patch: http://www.spinics.net/lists/arm-kernel/msg115817.html I'm handling all the c15 registers listed on p 4-11 of the Cortex-A9 r3p0 TRM. Would you please give me a reference for these other two registers? I'm not seeing them. Thanks. --Mark