From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([140.186.70.92]:57186)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <i.mitsyanko@gmail.com>) id 1RjEfJ-0000tr-2T
	for qemu-devel@nongnu.org; Fri, 06 Jan 2012 13:37:22 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <i.mitsyanko@gmail.com>) id 1RjEfI-0000vV-56
	for qemu-devel@nongnu.org; Fri, 06 Jan 2012 13:37:21 -0500
Received: from mail-bk0-f45.google.com ([209.85.214.45]:57166)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <i.mitsyanko@gmail.com>) id 1RjEfH-0000vG-Rz
	for qemu-devel@nongnu.org; Fri, 06 Jan 2012 13:37:20 -0500
Received: by bkbzu5 with SMTP id zu5so398269bkb.4
	for <qemu-devel@nongnu.org>; Fri, 06 Jan 2012 10:37:18 -0800 (PST)
Message-ID: <4F073F5E.6090507@gmail.com>
Date: Fri, 06 Jan 2012 22:37:18 +0400
From: Igor Mitsyanko <i.mitsyanko@gmail.com>
MIME-Version: 1.0
References: <1325793761-10249-1-git-send-email-mark.langsdorf@calxeda.com>
	<1325793761-10249-6-git-send-email-mark.langsdorf@calxeda.com>
In-Reply-To: <1325793761-10249-6-git-send-email-mark.langsdorf@calxeda.com>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH 5/5] arm: SoC model for Calxeda Highbank
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Mark Langsdorf <mark.langsdorf@calxeda.com>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Rob Herring <rob.herring@calxeda.com>, afaerber@suse.de

On 01/06/2012 12:02 AM, Mark Langsdorf wrote:

Hello, Mark. According to technical specification on Calxeda website, 
highbank SoC has SD 3.0 host controller, are you planning to implement 
it in qemu? I'm asking because I recently have submitted a patch 
implementing SD 2.0 host controller, and it looks like these two 
specifications revisions are not very different from each other.

> +    if (!cpu_model) {
> +        cpu_model = "cortex-a9";
> +    }

Google said there is only cortexA9-based Highbank SoC version, maybe you 
should just hardcode cpu model?

> +    /* Override default RAM size */
> +    if (ram_size == 0x8000000) {
> +        if (sizeof(long) == 8) {
> +            ram_size = 0xff900000;
> +        } else {

This value looks a bit strange, usually DRAM consists of several banks 
512, 256 (or something like that) megabytes each, I couldn't find what 
DRAM configuration does the actual board have?