From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59322) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl0JR-0000kq-Or for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:42:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rl0JJ-0004w5-Sg for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:42:05 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39034 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl0JJ-0004vo-Kl for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:41:57 -0500 Message-ID: <4F0DAD5E.4060702@suse.de> Date: Wed, 11 Jan 2012 16:40:14 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1326213943-878-1-git-send-email-mark.langsdorf@calxeda.com> <1326295570-10060-1-git-send-email-mark.langsdorf@calxeda.com> <1326295570-10060-3-git-send-email-mark.langsdorf@calxeda.com> In-Reply-To: <1326295570-10060-3-git-send-email-mark.langsdorf@calxeda.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Langsdorf Cc: i.mitsyanko@gmail.com, peter.maydell@linaro.org, qemu-devel@nongnu.org, edgar.iglesias@gmail.com Am 11.01.2012 16:26, schrieb Mark Langsdorf: > Increase the maximum number of GIC interrupts for a9mp and a11mp to 102= 0, > and create a configurable property for each defaulting to 96 and 64 > (respectively) so that device modelers can set the value appropriately > for their SoC. Other ARM processors also set their maximum number of > used IRQs appropriately. >=20 > Set the maximum theoretically number of GIC interrupts to 1020 and > update the save/restore code to only use the appropriate number for > each SoC. >=20 > Signed-off-by: Mark Langsdorf Reviewed-by: Andreas F=E4rber Andreas > --- > Changes from v7 > Removed unnecessary vmstate_register > Changes from v6 > Removed trailing whitespace > armv7m_nvic uses num_irq properly > Some comments changed > Changes from v5 > Clarify the commit message > Rename GIC_NIRQ to GIC_MAXIRQ and change usage slightly > Makes num-irq to uint32_t in all cases > Clarify the error message > Clarify documentation on the num-irq qdev property use in all f= iles > Changes from v4 > None > Changes from v3 > Increase maximum number of GIC interrupts to 1020 > Remove SoC/implementation specific GIC_NIRQ #defs > Added properties code to arm11mp > Changed error handling for too many interrupts > Redid save/load handling > Changes from v2 > Skipped > Changes from v1 > Increase the number of a9mp interrupts to 192 > Add a property defaulting to 96 > Add a num_irq member in the gic state structure > Use the num_irq value as appropriate > Add num_irq argument to gic_init() > Add num_irq to various CPU calls to gic_init --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg