From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RlTZn-0003mm-PP for qemu-devel@nongnu.org; Thu, 12 Jan 2012 17:56:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RlTZl-0003CG-V1 for qemu-devel@nongnu.org; Thu, 12 Jan 2012 17:56:55 -0500 Received: from e7.ny.us.ibm.com ([32.97.182.137]:57979) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RlTZl-0003Bp-RD for qemu-devel@nongnu.org; Thu, 12 Jan 2012 17:56:53 -0500 Received: from /spool/local by e7.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 12 Jan 2012 17:56:51 -0500 Received: from d01av03.pok.ibm.com (d01av03.pok.ibm.com [9.56.224.217]) by d01relay07.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q0CMulE53133646 for ; Thu, 12 Jan 2012 17:56:47 -0500 Received: from d01av03.pok.ibm.com (loopback [127.0.0.1]) by d01av03.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q0CMulD5009974 for ; Thu, 12 Jan 2012 20:56:47 -0200 Message-ID: <4F0F652E.6010307@us.ibm.com> Date: Thu, 12 Jan 2012 16:56:46 -0600 From: Anthony Liguori MIME-Version: 1.0 References: <1326390853-1892-1-git-send-email-aliguori@us.ibm.com> <4F0F4361.10201@codemonkey.ws> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] build: fix target_phys_addr_t to 64-bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org On 01/12/2012 04:46 PM, Peter Maydell wrote: > On 12 January 2012 22:42, Peter Maydell wrote: >> You're the one changing what was previously a known-to-be-32-bit >> type to one that's much bigger, you get to fix the printing >> issues. This code is broken in its current form. target_phys_addr_t has an unspecified width which is why we provide a FMT for it. Assuming it's 32-bit is just as bad as assuming that all hosts are 64-bit or all guests are little endian. It may have worked up until now for a particular device, but it doesn't change the fact that it was wrong. > ...which isn't to say that I don't think this is a good > plan (indeed I suspect I'm going to need wider physaddrs > for Cortex-A15 at some point :-)), just that I think we > ought to have at least a sketch of how the average device > for which the offset is going to be<4096, I think a reasonable thing to do is: #define PRIp64 "0x%08" PRIx64 s:TARGET_FMT_plx:PRIp64:g Then in places where desired, you can just use PRIx64 directly to specify a custom width. But that's a touch-everything change that I think should be done in a separate series. > let alone<32bits > can print messages involving the offsets without it looking > really ugly in either the code or the output (and that > where in this patch you're actually touching output formats > you should use whatever the reasonable-looking thing is > rather than just something that compiles.) To print a target_phys_addr_t, you need to use TARGET_FMT_plx. If code wasn't using TARGET_FMT_plx, then it was broken. If you want something more flexible than TARGET_FMT_plx, I'm supportive of that, but that should have been done to begin with instead of making bad assumptions about sizeof(target_phys_addr_t). Regards, Anthony Liguori > -- PMM >